converting jpeg file to ceo file

converting jpeg file to coe file

how to convert a jpeg image to .coe extension image. i have problem in initializing an image file to nexys2 board.
can u please help me....

Did you mean .coe ?

Re: converting jpeg file to coe file

blooz said:

Did you mean .coe ?

Click to expand...

yes sir.... i wanna convert my .jpg image to .coe image...
and to load this .coe image into the block RAM as initial data.

COE file Syntax
h**p://www.xilinx.com/itp/xilinx10/isehelp/cgn_r_coe_file_syntax.htm



---------- Post added at 19:59 ---------- Previous post was at 19:47 ----------

the Jpeg file format
h**p://en.wikipedia.org/wiki/JPEG

h**p://l1032265.myweb.hinet.net/huffman.htm

h**p://www.w3.org/Graphics/JPEG/jfif3.pdf

nexys 2 VGA contoller

sir, its showing an error...
i cant dump this .coe file to fpga...
using EDK software i wanna give an image to fpga through serial port RS232 providing a SDRAM

nenavath said:

using EDK software i wanna give an image to fpga through serial port RS232 providing a SDRAM

Click to expand...

And it took you 10 days to type up that little part of the specification? Guess I'll be checking this thread somewhere in March then. With a bit of luck you may have given a full description of what you want by then! XD

sry
i had attend for GATE exam, so it has been late...

No problem. I'm just suggesting you may want to provide more details. AFAIK we don't have any mind readers present on the forum.

Using xilinx platform studio embedded development kit(EDK), initially VGA peripheral should be configured,then to display images existing in PC to VGA through RS232(serial) communication.

MY board configuration is: XILINX 11.1 version

family: spartan 3E starter board
XC3S500E
package: FG320
speed grade: -4

sir i have given u the ful theme of my project...can u plzz help me.....:sad:

I have a review on this project on 20th of this month.can anyone pls help me....

Trying to bait me to this thread with a "Helpful post rating"? You clever little monkey you!

Couple of points you are free to ignore:

A review date is noone's problem but yours. Time management is such a wonderful thing. I know this because by nature I totally **** at it. But for some reason or other it seems time management is a very useful skill to have as an engineer. Besides, it's a review. Just cook up some bullshit argument why it's not done yet to buy you some time, and then you have another week to do the proper work. Thera ya go!

I totally ignored the post because while you may think you have given all the details, you only sortof have. So I was hoping someone else was willing to go through the totally obvious future back and forth of "here, this is the solution for the problem you specified. --- Nono, I need also a blinkenlights. --- Okay, here is a solution for a blinkenlights. --- Oh yes, and I also need to update the blinkenlights over RS232. --- etc".

What am I on about?

First you only mentioned you needed a .ceo file


Then 10 days later you come up with:

nenavath said:

using EDK software i wanna give an image to fpga through serial port RS232 providing a SDRAM

Click to expand...

So who knows what you will come up next. ;-)

And IFF I understand your requirements correctly, these are two entirely seperate problems. For convenience I am assuming you don't actually mean a .ceo file but do in fact mean a .coe file. Right? Right.


There, an example .coe file which incidentally is literally the first one I found in some test project directory I had. As you can see it's totally easy to read and generate using whatever tool you fancy. I'm sure xilinx may even have some tools for it. The careful reader may or may not note that the comment in this particular header may or may not be pedagogically sound at this point in time.

The .coe file is the easiest. All the .coe is, is just a static file that gets used during synthesis. So during synthesis the xilinx tools read the .coe and use that to bram initial data in the bitstream. Then during configuration (when your .bit file is put in the fpga) the actual data is stored in the BRAM. That is easy enough that you should get it working before the 20th, assuming you have the rest already working. Oh wait, psychology, yeah right sorry, my bad! Disregard that false hope I just gave. Do not disregard the fact about this being the easiest part however. The point there is to get the .coe business working first, and only then start worrying about your RS232 stuff.

What RS232 stuff? Oh the RS232 stuff you made up 10 days after you gave the initial problem. Do you read Dilbert?

So the RS232 stuff ... If I understand you correctly you want to first initialize it with a .coe file. That way whenever you powerup the device and it configures then it will show the initial picture based on the data in that .coe file.

And then AFTER the powerup you want to be able to send it updates with new picture data. Yes? Cool. That's an entirely different thing, which incidentally is also more work than just the static pic from the .coe file. What you need here is some way to update your BRAM content, and apparently by using RS232 link.

So you'll need an UART + a small FSM to do the BRAM updates for you.

If "yes" you do need the static pic AND the updates as I'm guessing from your posts, and "no, I don't know what the hell you are on about with that UART + FSM" then I suggest forget that until the 21st. Just get a static pic working so they can go "ooooooh aaaaaah static pic!" during the review. And then after that worry about getting an UART + FSM working.

Possibly you could also use chipscope to do quick and dirty bram updates IF you are already familiar with it. If not then the UART + FSM is faster. That, and it will pass a final review, which I doubt any chipscope solution will.

Oh yeah, one last quick tip. I assume you want to do updates AND still be able to show the pic at the same time. Which means you will still be doing BRAM reads (to show the picture) while at the same time you want to do BRAM writes (to update the picture). If so, you want to make this a dual port BRAM with a read and a write port.

---------- Post added at 17:41 ---------- Previous post was at 16:50 ----------

Since certain very specific locations sometimes have google outages here's one google hit by proxy:

Initializing BRAM via CoreGen File Size Problem - Xilinx User Community Forums

thanks for ur reply...

sorry sir if u are confused...

actually i am doing a project related to this attachment. if u watch this link, propably u may come to knw exactly wat i am doing...

No worries. I am perpetually confused, so that's no fault of yours.

Just wondering, any particular reason to provide this PDF now? You know, instead of 14 days ago?

I mean the pdf is a dead giveaway this is a homework assignment, but we all knew that anyways.

Anyways, a quick quick glance at the PDF in 1 minute didn't give me more ideas. So I guess it's time for you to do some work. gogogo. If you have specific code + specific questions, by all means post your code and question.

mrflibble said:

No worries. I am perpetually confused, so that's no fault of yours.

Just wondering, any particular reason to provide this PDF now? You know, instead of 14 days ago?

I mean the pdf is a dead giveaway this is a homework assignment, but we all knew that anyways.

Anyways, a quick quick glance at the PDF in 1 minute didn't give me more ideas. So I guess it's time for you to do some work. gogogo. If you have specific code + specific questions, by all means post your code and question.

Click to expand...

thanks a lot....

Good luck! If you have specific code you have done so far with specific problems, feel free to post.

hi .... this is praveen
am also doing same type of project ..

am writing code for image enhancement.
first am taking simple negative transform.
now am try to implement it on hardware.


my doubt is "how to generate .coe file from jpeg/bmp."

is it directly come by giving image file to rom/ram using xilinx_ip_core...
or by using matlab ..

am read the .coe file link .. but i didn't understand it..

please give some suggestion.

praveenvanaparthy said:

please give some suggestion.

Click to expand...

Okay. I suggest you please take the time to write a problem description we can understand. I barely follow what you mean.

For your problem, can we forget about the entire image stuff? Is your only real problem the following: "help I have some bits, now how do I get them in a .coe file so that those bits will show up inside of my fpga"?

If yes, don't just say "yes", but tell us what the exact problem is. Because it could be that your software gives you an error (which error) and it could also be that you haven't bothered reading documentation (go read the docs).

And if it's something else, then what?

So in short I suggest: clarity.

- - - Updated - - -

Did a quick check of your other posts. They seem to be more of the same. So how about you give us a list of urls for the documentation you read on how to do .coe files.

Because I postulate you should RTFM and it shall solve all problems.

k ..

please tell me how to convert an image to a .coe file.