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vhdl or verilog which is better to program FPGA

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ya if you are beginner then programming using verilog is good try to study programmable devices spartan 3E u can get the pdfs
 

It depends...
If you have good C programming skills - go with and don't look back.
However, if you prefer strict rules and a VERY strongly typed language - go with VHDL.

Also,
You should consider your goals.
If you're learing FPGA design with an intention on working in that field - you should choose the HDL that dominant in your country.
 
yup i am pretty good in C language ;)
and more over i wanna make a project FPGA based modulator n demodulator ... so i suppose VHDL will help me in the long run ...isntit ?
 

Anything you can implement in VHDL you can do in Verilog and vice versa.
more than 70% of VHDL is intended for simulation only and is unsynthesizable syntax.

Intel uses Verilog for their CPUs...
I use VHDL myself and not Verilog because it's the first HDL I learned.

Start with VHDL - It's extremely VERBOSE and VERY strongly typed. But that will help you acquire good coding skills and correct design methology.
Then when you get more confident, move to Verilog. The transition will be easier then doing the opposite.
 

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