pavithra226
Member level 1
how to fix maximum capacitance violation, max transition violation using cadence encounter
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@yadav: am getting these viloations at the sign-off stage affter adding bufers to componsate transViolation. So, does deleting these nets causes deleting any of those buffers added?
Also how to fix SI(signal integration) errors?
Why do you want to clear the fanout violations?
These violations did not involve in timing liberty table.
# Delete the nets having DRC violations
editDeleteViolations
#Reroute deleted nets
ecoRoute
You can try this multiple times.