Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

why do we need to give source clock while defining generated clock?

Status
Not open for further replies.
E

electronab

Newbie level 2
Newbie level 2
Joined
Dec 17, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
why do we need to give source clock while defining generated clock? Is it just for getting divide_by information or something more. what relationship maintained between the two. For below mentioned two cases -

CASE1 - We do not want to balance master clock and its generated clock.
CASE2 - What if there is another master clock in between master-clock-1 and generated clock (generated from master-clock-1). How would the tool behave?

(I am thinking in terms of physical design tool)
 
Last edited:

The sta will know the relation between the source clock and the generated ****, and could be considered as synchronous.

---------- Post added at 09:06 ---------- Previous post was at 09:06 ----------

instead two create clocks, that are considered as asynchronous.
 
What if there is another master clock in between master-clock-1 and generated clock
Click to expand...
What do u mean? wanna elaborate?

could be considered as synchronous
Click to expand...
Is it possible to define a latency for the generated clock?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top