load *.txt file into fpga

Dear all,

I have convert an image into a matrix and save them as *.txt file. Then, the matrix will be send into FPGA and will be stored in RAM. My question is, how to load the *.txt file into FPGA? As I know FPGA cannot do any file IO for synthesis. Is it any ways to load the matrix data? Need helps..thank you

Hi

If you want to do some image processing using fpga ,you need some sram or sdram which is interfaced with fpga.

FPGA will have less BRAM to download a image.

if you choose xilinx fpga you can use xilinx edk software where you can do some image procesing in c language and implement it easier

let me know the application

ignore the text file. The data will be raw data. You will need an IP core to send the data from PC to FPGA - something easy like a serial link, or harder like ethernet or USB (Altera provide ethernet core for as part of a paid licence).

Hi all,

jeevarajan.mk > yes I do an image processing using fpga. I use DE2 Altera board as my hardware implementation.

TrickyDicky > How to ignore the text file? I can't get what you say. The image matrix is save in *.txt file and will be load into fpga via rs232 cable.

Thank for reply..

you wont load a text file into the FPGA. You'll be loading raw data. The FPGA has no knowledge of it being a text file, or binary file, or exe file, its just raw binary. You will need a uart to load it into SD ram like jeev said (or you could just use the data as it arrives).

Well, if the file you are referring has a size of few hundred kilobytes then you can use a simple UART interface between a PC and your FPGA unit. Use some apps developed in VB\C to transfer your image file from PC to FPGA in UART serially at high baud rate. In FPGA, you need to write some glue logic to read UART raw image data bytes and store in internal RAM\external flash depending on ur reqmts.

But be advised, since it is UART it can consume huge time. I did image display prj in Mini LCD of size 240x320 with 18bits per pixel. In this case we transferred image text file each of size around 200KB in some 9 secs time at 115baudrate. But it was our requirement and we had 10 sec affordable time between next image. Check your requirement.

Loading of text at synthesize isn't possible, however loading of ROM contents is possible using editor in IP wizard, but you cannot process realtime data though.

hope it gives little clarity :idea:

Hi all,

I have write the code for SRAM entity to stored the image matrix data with input declaration of std_logic_vector (row binary data).What I am confusing here is how fpga will get the row data of the image matrix since the row data is in a text file(fpga can't read/write file). I really can't imagine it..can anyone figure it out or explain the process start from image-matrix-row data-fpga? Maybe my question looks simple to you,but I need more guide with this matter.. thanks for your response..

From your point what I understand is that you want to read data from file and do matrix processing and store result in SRAM, rite?. If so, ok, first we must be clear with your input format. What exactly you mean by matrix?. Is it a jpeg data taken matrix or any other format?. If so, can you post here? (I mean the matrix text file). Also tell what will be your input data type and width for your matrix operation?. Are you doing any matrix operation inside FPGA or just SRAM write?.

Hi xtcx,

Yes rite, I want to read data from file and store in SRAM..

1. I convert the image into matrix form in Matlab where this matrix will be my input to fpga and stored in SRAM.

1. The size of the matrix is 512x512..but I want to process the matrix by 4x4 until end (partitioning).

1. Yes, I do a matrix operation inside FPGA by call the value from the SRAM.

I declare the input data type as sfixed and all the operation also in sfixed data type. So,I need to convert the matrix (integer) to sfixed, rite? I attach the matrix file, hope you get my point..thanks for reply..

have you got your code working in simulation yet? I suggest you get it ALL working in simulation before trying to do it on an FPGA.

Hi TrickyDicky,

Not yet for the simulation,still writing the code. Btw, can you give any idea on how to write code for the partitioning matrix in vhdl? How to start read 4x4 matrix, until end (512x512)? Is it possible to do like that?..thank for reply..

what you want to do is perfectly possible, but its quite advanced HDL design.

Have you started your basic VHDL and Digital logic design course yet? when you've completed that, and had a year's work experience with VHDL, you might be able to do what you want.

Hi TrickyDicky,

I have take digital logic design course a few years back. I have no experience with VHDL (writing for advance/complex project). That's why I try to get an idea how to start. Your word "its quite advanced HDL design" really make me worried,can I do this in time..:sad: btw,thanks for reply

Dear fanwell

I can help you to load txt file if you choose any xilinx board with sdram or ddr ,i have no knowledge in altera tools.

Hi fanwell
Is your problem
How to send data from file to FPGA? or how to process 4x4 matrix from a 512x512?.

Arrange your 4x4 matrix. Create a 4x4 structure in ur design in which write the SRAM data something like
m(n+0) m(n+4) m(n+8) m(n+12)
m(n+1) m(n+5) m(n+9) m(n+13)
m(n+2) m(n+6) m(n+10) m(n+14)
m(n+3) m(n+7) m(n+11) m(n+15) (where n=0 to 496)


1) Use an offset value which will access memory in terms of 4x4. In this case offset is n=16. Read 16 data elements and then process. Then add offset value (16+16) = 32, then process 2nd 4x4 matrix. Proceed like this using a state machine until you n=496. This will be your last 4x4 in your 512x512

2) coming to your input type, you said sfixed,is this a floating point matrix?. Also I doubt if sfixed() is synthezisable in Xilinx edition as I heard from someone. Check the package you are using and make sure. Also you cannot read as integer type from SRAM though the actual data may be an integer. But I believe since you have taken from matlab, from my knowledge, the elements could be in 2's complement. Please check this and make sure. On that case, add library as ieee.std_logic_signed.all. If you are using this library, the all std_logic_vector behaves as signed and sign will be preserved. Beware!!. Or simply use signed().

ok use std_logic_vector as input for reading SRAM content. The values of matrix u have shared seems to be 12-bit for each element (0 to 4080) and not more than tat. IF this is going to be your max/min integer value then use 12-bit as your data bit width.

3) As for your file read, you must use some hardware interface between host PC and FPGA like UART\USB\Ethernet. Also there are some tools which can write data into DDR\Flash using USB\UART provided the board must have such features like what jeevarajan.mk said.

See which is easy for you, then you can think about sending and receiving matrix data.

Hope it clears a bit....:!:
Cheers.

Hi all,

jeevarajan.mk > I am using Altera DE2 board since it provided in my uni. Btw, thanks for your concern.

xtcx > My problem is both. First, how to process 4x4 matrix from 512x512 matrix where this matrix is from a file created in Matlab.
Second, how to send the data (matrix) from file to fpga. Thanks for your idea, I will study on that. Thank you very much..

Hi all,

I attach code for memory where datain shows ZZZZZZ in ModelSim simulation. (related to my previous post but doesn't appear here.Don't know why).
Hope you can tell me where my mistake..thank you

Hi all,

I attach code for memory where datain shows ZZZZZZ in ModelSim simulation. (related to my previous post but doesn't appear here.Don't know why).
Hope you can tell me where my mistake..thank you

After I looked at your code, I replied that ZZZ will only occur is CS = '0' or CS = '1' and wr or rd = '0'. Also, why have you got 'ZZZ' as an option, as dataout is an output, not an inout, and so 'ZZZ' is a pointless output.

I assume you understand this code is only a simulation model and cannot be synthesised.

TrickyDicky said:

After I looked at your code, I replied that ZZZ will only occur is CS = '0' or CS = '1' and wr or rd = '0'. Also, why have you got 'ZZZ' as an option, as dataout is an output, not an inout, and so 'ZZZ' is a pointless output.

I assume you understand this code is only a simulation model and cannot be synthesised.

Click to expand...

Yes I understand this code is only for simulation. I try to get an idea on how the data file is read from this code. I try to modify the code by replace the input file with std_logic_vector(7 downto 0). Where the first input file's value is read. But the simulation shows an error. Can you give any idea to synthesised this code..thank for reply