Real World Sizing of Inverters

Hi,
Why the sizing of transistors in real world sizing are in the ratio 1.5 : 1 ? The books i refer uses 2:1 ratio for Width of Pmos to Width of Nmos ratio.
Thanks in advance.

In CMOS, PMOS is used as pull up device while NMOS is used as pull down. If you wants to have equal rise and fall time for a cell, you need to have equal pull up and pull down resistance. In PMOS majority carriers are holes while in NMOS majority carries are electrons. Electron mobility is nearly 2.5 times grater than holes. So PMOS is made wider to compensate this at the cost of area. You can have PMOS 2 times wider in case of a inverter & buffer and get equal rise and fall time. But if you consider multi-input gate, say 2 input NAND gate, It has two PMOS transistor in parallel while two NMOS in series. So the the worst case is when both NMOS are ON as resistance in series will increase. So there is no advantage of making PMOS 2 time wider as two NMOS in series resistance will have more resistance.

Hey,

Sizing is always done as per requirement and mobility ratio of PMOS and NMOS. Moreover, it also depends on what is the minimum feature size available in that technological node.


BR//
Abhishek

Depending on the rise time and fall time requirement of output, the sizing differs.