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leading edge blanking for pwm chip

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hi. how to implement leading edge blanking circuitry in SG3526 pwm chip which has two outputs. it has to be operated in fullbridge with current sense resistor at bottom side.
 

In designing other Unitrode-compatible PWMs I recall this being an internal feature
without much user access. Idea being to prevent false early end-of-cycle from
switch ringing (but getting the ringing to damp within LEB window, is on you).
 

Hmm, I don't see any way to implement it on that controller. It doesn't give any user access to the logic controlling the internal latches. If you absolutely need blanking, then you should find another controller that offers it.

edit: well, to clarify there are ways to effectively get LEB, but it has to be done by modifying the current sense signal, rather than the internal state machine. Basically you just need to inject a pulse into the input of the CS comparator at the start of each switching cycle. It's kind of messy, but if you're interested then I can go into detail.
 
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mtwieg said:
well, to clarify there are ways to effectively get LEB, but it has to be done by modifying the current sense signal, rather than the internal state machine. Basically you just need to inject a pulse into the input of the CS comparator at the start of each switching cycle. It's kind of messy, but if you're interested then I can go into detail.
Click to expand...

I know one design idea published by Michael O'loughlin of TI. if your idea is different then please proceed. I have attached his idea.

You will notice that his formulas to calculate values is correct but his calculation for his example is misleading and seem not correct.
 

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