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[SOLVED] Is it possible to layout a BGA484 on a one layer PCB?

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elockpicker

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Hi,

Is it possible to layout and assemble a BGA-484 IC on a one-layer PCB (only two signal layers and no image planes)?
If possible, is it a good idea?

Thanks very much
 

Possible, yes, but I wouldn't recommend it. If this is a high-speed device, you really need to have a ground plane. Why would you take a relatively expensive BGA device, and then scrimp on your PCB? It's like driving a Ferrari on a dirt road.
 
Pay attention to high speed signal.You'd better use 4 layer, top-signal,inner1-gnd,inner2-vcc,bottom-signal. Good luck for you
 
Thank you very much,
It is not a high speed board (maximum clock freq = 50MHz).
But if, for what ever reason, I am obliged to use the one-layer board then in order to connect tracks to the IOs (BGA) I should use some through-hole vias beneath the IC surface, right?
 

If you are sending this out to a fab house, the minimum number of layer is usually 2. The number of layers goes in increments of 2. Typically, a PCB has 2,4,6,8 etc number of layers so there is no reason for you to use one layer board unless you are fabricating this yourself.

Microwave123
 

elockpicker;1009897It is not a high speed board (maximum clock freq = 50MHz).[/QUOTE said:
It's not just the speed, it's the edges which will cause ringing, etc. Without a low impedance ground plane the noise caused by switching signals will be coupled into other areas of the board. Just don't do it.
Click to expand...
 
No chance, it wont work. How are you going to get power to the device, instantaneous switching currents are very high, tens of amps. How qare you going to decouple the power pins! And signal integrity will go out of the window, as well as EMC problems. You require a return path for all the signals so you need ground planes. And 50MHz is high speed, you will have harmonics into the low GHz's probably, depending as Barry said on your rise time. Look up Knee frequency.
**broken link removed**
Printed Circuit Design & Fab Magazine Online
 
Thank you very much, you really did help me.

but one question, "tens of amps" ?!
isn't it probably tens of miliamps?
 

I'm suprised nobody has mentioned trying to fan out 484 balls, its normally a layer for each 2 rows...
 

Ref the links to Charles Pfeil, the book covers all aspects of BGA breakout, hence the link, its a good basic guide to BGA brakout and free...
When switching there is a very very very finite time where the rails are effectively shorted.
 

Besides the said 50 MHz clock speed,, your posts are missing all informations to determine if your intention may work in this case, e.g. number of IO lines, number of supply rails, required respectively intended supply bypassing. Also PCB density plays an important role. I guess limiting the design to a dual layer board (which is apparently meaned with one layer PCB, if I understand your post right) also implies very basic density, e.g. 6 mils/150 u structure size. In this technology, you have even problems to route a single trace between 1 mm grid balls or vias.

Personally, I have used 484 pin BGA at minimal 4 layer boards, but it was only possible due to a rather sparse pin utilization. Under normal conditions, 6 layers and 4 mils/100 u structure size is minimum for 484 pin BGA (with 1 mm ball grid).
 

Thank you,
My question was the possibility of mounting a BGA484 rather than the EMC an SI issues.
I am already convinced to use the multilayer boards.

However, here are the info that were missing:
The IC is one of the Actel's low power FPGAs : M1AGL1000
The clock oscillator will produce a 5MHz clock (maximum) but I might be using the internal PLL and gguide the higher speed clock out of the FPGA.
The board is not crowded at all. Only a few small ICs besides FPGA.
I'll be using at most 20 of the IOs.
About the bypassing: I do not currently have any experience designing a FPGA board so I'm sticking to the evaluation board schematics by Actel which includes over 20 bypass capacitors.
It would be great if you show me some material about choosing the bypass caps too.

Thank you very much in advance.
 

20 bypass capacitors sounds reasonable in general. Considering your very low IO count, fewer are most likely O.K., particularly for the IO supply voltage rails. Required core voltage bypassing is more dependant on logic activity and maximum clock frequency, PLLs are a matter on it's own. Insufficient PLL bypassing can easily cause design failure.

I presume, that the reference design's bypassing scheme is based on a continuous ground plane and most likely also power planes or at least larger power isles for the individual supply nodes. This is most likely infeasible in double layer PCB. Because many supply pads are located in the BGA center, placing small bypass capacitors, e.g 0402 size on the bottom side below the FPGA would be the best solution.
 
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