[SOLVED] What is sensitivity list in VHDL?

I was reading some book on VHDL and I came across this term. What do you mean by sensitivity list?

Thanks in advance.

Sensitivity list is what triggers process entry.
For example:

--------------------------
process(clk, rst) is
begin
if rst = '1' then
a <= '0';
elsif rising_edge(clk) then
a <= b;
end if;
end process;
--------------------------

"clk" and "rst" are the signals in the sensitivity list.
Hence, the process is "entered" with any CHANGE in these signals.
For the above process: a change in reset ("rst") signal will cause a process entry, as well as any change in clock ("clk") signal.
It simply describes a 'D' flip flop with an asynchronous reset...

Well explained by shaiko. Check this link also.
**broken link removed**

Hello.
What happen when a signal in sensitivity list change value twice while the process is in motion?

for example:

process(clk, reset) is
begin
ABC <= ABC + 1;
-------
--some lengthy process
-------
end process;


When clock changes value from '0' to '1', the process will resume execution. But while executing, say, clk changes from '1' to '0' and then again from '0' to '1'.
Will the process execute again twice after current process finishes or not at all (because clk has the same value '1' from previous check)?

There is no guarantee that a process will be done before a signal in the sensitivity list changes again right? Please help me clarify this.


Thanks in advance!

dave_xenos said:

Hello.
What happen when a signal in sensitivity list change value twice while the process is in motion?

Click to expand...

That can't happen because...

for example:

process(clk, reset) is
begin
ABC <= ABC + 1;
-------
--some lengthy process
-------
end process;

Click to expand...

There is no such thing as 'some lengthy process' if the process has a sensitivity list.

When clock changes value from '0' to '1', the process will resume execution. But while executing, say, clk changes from '1' to '0' and then again from '0' to '1'.
Will the process execute again twice after current process finishes or not at all (because clk has the same value '1' from previous check)?

There is no guarantee that a process will be done before a signal in the sensitivity list changes again right? Please help me clarify this.

Click to expand...

Yes there is a guarantee. A process with a sensitivity list will always complete exactly one 'delta cycle' after it started. A 'delta cycle' is an infintesimal delay. You can think of it as femtoseconds or something even smaller if you'd like but it has no actual 'time' units.

The only way you can have 'some lengthy process' is if the process has some form of wait statement in it like the following:
- wait for 1 us
- wait until (this = that);
- wait on this_signal
- wait until rising_edge(clock)

It is an error (and the compiler will flag it) if you have a process with a sensitivity list and then try to use any form of wait statement. So, if a process with a sensitivity list cannot have any form of 'wait', then it implies that such a process must complete exactly one delta cycle after it starts up. The compiler error that prevents you from writing such code is your guarantee.

Kevin Jennings