CMOS voltage swings (minimum, maximum) confusion

Hello,

I can't figure out a fool proof way to determine the minimum and maximum output voltage swing of a CMOS circuit. I really don't see it.
Take this example.



I know that for saturation, |VDS| > |VGS| - TH
So I guess for NMOS it means that the drain voltage can maximum be a treshold under gate voltage.
I think that the VGS has to be at least the treshold voltage + overdrive voltage ?
For the PMOS it is the same but opposite signs.
Is there a fool prove way to find the voltage swings? I've broken my mind many times over it.
From the example, the maximum voltage is VDD-VGS3+VTH1. I guess they are driving the drain voltage of M3 one treshold voltage higher than the gate voltage. But why VTH1 and not VTH3?

I'm trying to determine the minimum and maximum of vout.
I've found so far:
-Minimum: Vout = Vcss + Vgs2
-Maximum: Trying.... (M3 and M4 form current mirror, so VGS4 is fixed) so i think: VDD-VGS4+VTH4
please correct me if I'm wrong



Thanks in advance.

The_Dutchman said:

From the example, the maximum voltage is VDD-VGS3+VTH1. I guess they are driving the drain voltage of M3 one treshold voltage higher than the gate voltage. But why VTH1 and not VTH3?

Click to expand...

M1 goes in triode region when Vd1 is lower then Vgs1 by Vth1 --> Vgs1 = Vd1 + Vth1.
Vd3 (and Vg3) are always fixed at Vdd-|Vgs3| (M3 works as a "diode").
Since Vd1=Vd3, you have Vd1=Vdd-|Vgs3| --> Vgs1 = Vdd - |Vgs3| + Vth1

Hi The_dutchman!
Your strucutre is type N with M1,M2: differential pair, M3,M4: Load and normally, you have M5 is the current source. Then common mode input range < for Opamp: satisfy all transistor operate in active region>:
Vicmin = vov5 + Vgs3
Vicmax = Vdd + Vt1 - Vgs3
therefor: Vt1 + Vov1 + Vov5 ≤ Vic ≤ Vdd - Vt1 - |Vt3| - |Vov3|

Also, you can try with the structure type P, you will see some interesting results. In more details, the structure type P will has better output swing than type N.

Hope this help!