Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why no filler cells in netlist when doing LVS ?

Status
Not open for further replies.
O

owen_li

Full Member level 3
Full Member level 3
Joined
Jul 22, 2007
Messages
150
Helped
17
Reputation
34
Reaction score
15
Trophy points
1,298
Activity points
2,301
Hi.

When we are doing LVS in my current chip, we just write out the normal standard cells and decap cells into the final netlist, but ignore the filler cells.

However, LVS passed. I wonder why the filler cells are not dump into netlist ?

But the fillers are actually included in the GDSII file.

Thanks all!
 

The filler cells do not contain any devices - just M1 power rails and NWELL. So, nothing to compare during LVS.
 
owen_li
Fillers are added in the design to keep power rail and NWELL continuity. Also if design changes after BASE PG, then these FILLER can be replaced with ECO cells.

As oratie said, there is nothing to compare in FILLER. So NETLIST does not contain FILLER, but GDSII is the final deliverable and used for PG. Hence GDSII should contain FILLER info.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top