aria62
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After reading my VHDL code in "Synopsys Design Analyzer", when i compile the design
using command window, the following error appears:
"could not read following target libraries: (UI0-3) your_library.db"
I only use IEEE library. How can i link this library?
this is my VHDL code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_2_1 IS
PORT(mux_in1 : IN STD_LOGIC;
mux_in2 : IN STD_LOGIC;
mux_sel : IN STD_LOGIC;
mux_out : OUT STD_LOGIC);
END ENTITY mux_2_1;
ARCHITECTURE mux_arch OF mux_2_1 IS
BEGIN
PROCESS(mux_in1,mux_in2,mux_sel)
BEGIN
CASE mux_sel IS
WHEN '0' =>
mux_out <= mux_in1;
WHEN '1' =>
mux_out <= mux_in2;
WHEN OTHERS =>
mux_out <= 'Z';
END CASE;
END PROCESS;
END ARCHITECTURE mux_arch;
using command window, the following error appears:
"could not read following target libraries: (UI0-3) your_library.db"
I only use IEEE library. How can i link this library?
this is my VHDL code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux_2_1 IS
PORT(mux_in1 : IN STD_LOGIC;
mux_in2 : IN STD_LOGIC;
mux_sel : IN STD_LOGIC;
mux_out : OUT STD_LOGIC);
END ENTITY mux_2_1;
ARCHITECTURE mux_arch OF mux_2_1 IS
BEGIN
PROCESS(mux_in1,mux_in2,mux_sel)
BEGIN
CASE mux_sel IS
WHEN '0' =>
mux_out <= mux_in1;
WHEN '1' =>
mux_out <= mux_in2;
WHEN OTHERS =>
mux_out <= 'Z';
END CASE;
END PROCESS;
END ARCHITECTURE mux_arch;