physical design libraries

What are the different technological libraries that are required for physical design?
What are technology rule files?
Is their sometihng called time library,power library,noise library?

physical library: LEF file, techno lef which contains the technology rules for the metal layers, and LEF file for all stdcell/pad/memories/macro (in general) which describe the pin positions/obstructions/antenna.
power lib are inside LIBERTY files.
noise library come from cdb files.
RC data come from nxtgrd/captable files

can u please elobrate littel more. So that i get better understanding.

hai pavitra,
As rca said is right,

Technology rule file: -
Additional to that there is Technology rule for lvs and drc rule files will also differ according to the pdk..

library file :-
Basically lib file is divided into Worst case, bestcase and typical library file. (these three differs due to Process Voltage and Temperature (PVT))


worst case:-fast process, highest voltage and lowest temperature
Typical case :- mid of this..
Best case:- slow process, lowest voltage and highest temperature

In project level if u satisfy worst and best.. maximum typical case will also be satisfied...

Ex:-
libname_max_1p5v_125c.lib
Normally every lib file will be like this
Denoting max - process
1p5v - voltage
125c - Temperature

This may help... Thanks

1. Explanation about technology:
o Digital design is divided as Front end and Back end. Front end is the area where we design IP without considering the technology node (Ex: 65n, 28n...)
o Once the RTL is ready, we decide the technology. To implement the design IP in particular technology node, we need standard cell and its deliverable in that node.

2. Libraries:
o Libraries contain basic cell like NAND, FLOPS and Boolean functions.
o In Synthesis, RTL a technology independent code is converted into gate level netlist(Specific to the technology node)
3. Place and Route:
o During this process, tool picks the cells from library and place them.
o For placement and routing we need to know the routing data within the cell. This routing info is present in CORE LEF.
o For routing of metal and VIAs we need to have TECHNOLOGY LEF. In this lef pitch and VIAs will be defined considering lpad rules.
o Cells need to be placed considering the timing, this info is present in ".liberty" files.
o ". liberality" files are generated by characterizing the standard cells. Characterization means operating the cells at different load and slew and creating a file with these values. Which will be help full during RTL - GDSII for timing constraints.

does cdb stands for "compiler data base"

CDB is "celtic data base" model file for crosstalk noise analysis.

Usually there will not be separate library for noise . CCS libraries will have noise data as well. (As far as I know.). Rest well explained by @Vijay and @Somashekar in above posts.