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synthesis error in verilog code:

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priyanka24

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Hi..
am trying to implement unary code in verilog.i got the simulation results correctly.but when me doing synthesis as i want to see RTL view of my design i got error as follows:

"ERROR:Xst:2634 - "unary.v" line 29: For loop stop condition should depend on loop variable or be static."

my code is as follows.help me if can as to go further i need synthesizable code.


module unary(q,unary_out,unary_len);
integer j;
output reg [2:0]unary_len;
reg [2:0]seq;
input [1:0] q;
output reg [2:0] unary_out;
always @(q)
begin
for(j=1;j<=q;j=j+1)
begin
unary_out[j]=0;
end
unary_out[0]=1;
unary_len=j;
end
endmodule
 

Could you explain what your design should do? For what you've declared reg [2:0]seq;... where do u use it?
I think it would be better to use case statement for q... Elaborate your design, please..
 

You could not use a signal to control the size of your loop.
Your loop need to be fix from 0 to maximum of q value, and inside your loop you add a if(j<q) which contains what you have inside your current for.
 

yes thats correct me not using seq anywhere.but still the same problem occur in synthesis.
my code is generating q strings of 0's followed by 1.
suppose q=2 then my output should be 001.
so unary_out will give me output and how much bits is my output is seen by unary_len.
so plz help me if u get..
Alosevskoy said:
Could you explain what your design should do? For what you've declared reg [2:0]seq;... where do u use it?
I think it would be better to use case statement for q... Elaborate your design, please..
Click to expand...


---------- Post added at 11:36 ---------- Previous post was at 11:35 ----------
rca said:
You could not use a signal to control the size of your loop.
Your loop need to be fix from 0 to maximum of q value, and inside your loop you add a if(j<q) which contains what you have inside your current for.
Click to expand...

me not able to understand what u actually want to say.
 

As I see unary_len shows how many bits to take from constant output unary_out:

`timescale 1ns/1ps
module unary(
q,
unary_out,
unary_len
);
input [1:0] q;
output [3:0] unary_out;

output [2:0] unary_len;

assign unary_out = 4'b0001;

assign unary_len = q + 1;

endmodule // unary
Click to expand...

To tell the truth that design seems to me a bit strange :wink: Where it will be used?
 
Alosevskoy said:
As I see unary_len shows how many bits to take from constant output unary_out:



To tell the truth that design seems to me a bit strange :wink: Where it will be used?
Click to expand...

actually it is one module of my project 'golomb rice coding for data compression'.i have to implement it in verilog. this golomb rice coding is noting but RLE(run length coding). so this is one module of it but not getting the synthsisable code as i getting error in it.so plz help if u can....

---------- Post added at 17:38 ---------- Previous post was at 17:19 ----------
Alosevskoy said:
As I see unary_len shows how many bits to take from constant output unary_out:



To tell the truth that design seems to me a bit strange :wink: Where it will be used?
Click to expand...


here u hv fixed value of q fixed to value 2.but in actual it can be anything so in that case this program written by u is not valid.
 

here u hv fixed value of q fixed to value 2.but in actual it can be anything so in that case this program written by u is not valid.
Click to expand...
In my code q is not a fixed value, it can be 0, 1, 2 or 3... The output unary_out is constant, but unary_len tells how many bits to take from unary_out.
 
Alosevskoy said:
In my code q is not a fixed value, it can be 0, 1, 2 or 3... The output unary_out is constant, but unary_len tells how many bits to take from unary_out.
Click to expand...

i have tried your code also but its check syntax is fail and not showing which errors are present.
 

there are several issues with the original code. In better cases, it would generated undesirable latches. In more realistic cases, it would be removed entirely. Or in the actual case, be an error.

in either case, the type of unary_out is a 4b value. So you will get either 0001, 0001, 0001, or 0001. (or possibly xxx1, xx01, x001 at the start of sim). Just because you don't define an output for a given case doesn't mean it doesn't exist. It will just default to x <= x, which infers a latch in a combinatorial process, or is harmless in a clocked process.
 
permute said:
there are several issues with the original code. In better cases, it would generated undesirable latches. In more realistic cases, it would be removed entirely. Or in the actual case, be an error.

in either case, the type of unary_out is a 4b value. So you will get either 0001, 0001, 0001, or 0001. (or possibly xxx1, xx01, x001 at the start of sim). Just because you don't define an output for a given case doesn't mean it doesn't exist. It will just default to x <= x, which infers a latch in a combinatorial process, or is harmless in a clocked process.
Click to expand...

but actually what problem in my code and what i should do for it???????
 

What i meant was that you are looking for language features that do not exist in verilog/vhdl. they also don't exist in any programming language that I'm aware of. As such, your module doesn't work and will never work. had it not been a synthesis error, it would describe what is essentially a constant value, which is not what is intended. You need to go back to the drawing board and then come back with more questions.
 

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