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Recent content by Y.T_comp

  1. Y.T_comp

    What is the difference between the resolution and sensitivity in sensor science

    As-Salāmu `Alaykum 1 Hi all I have new question and I think this forum is the best place to this question . Anyway , I have a miss understanding about tow terms which are : sensitivity and resolution . I read from a NI website about them 2 ,and I didn't find a difference between them . But I...
  2. Y.T_comp

    INTEL manuals for 8086 and 8085

    https://www.mediafire.com/?mhf9o7ekd7uvo7y
  3. Y.T_comp

    Linux PCB, Schematic and Simulation solution!

    there is geda(GNU electronic design automating ). or simply use virtual box or VMware.
  4. Y.T_comp

    Designing a simple Common Emitter amplifier circuit.

    welcome :) Rac and Rdc is the equivalent resistance in emitter-collector circuit in dc/ac . for example for common emitter configuration \[R_{ac}=R_E + R_C || R_L . \] \[R_{dc}=R_E + R_C .\] if we consider that \[R_E\] is not bypassed by a capacitor and the load \[R_L\] is connected...
  5. Y.T_comp

    Designing a simple Common Emitter amplifier circuit.

    welcom Shayaan_Mustafa :) as I know you can't design amplifier without knowing some values like\[ R_E \]and\[ R_C\] and\[ \beta\] . when you have sufficient elements to design you can start. designing relations -which is true and used in design- are: \[ I_{CQ}=\frac{V_{CC}}{R_{ac}+R_{dc}}...
  6. Y.T_comp

    dealing with output in a shifter

    so it's true that the right signals on the assignment statement must br input or buffer or inout . thank you std_match for explanation .
  7. Y.T_comp

    dealing with output in a shifter

    HI all ! I have new question :-D, if I have a synchronised shifter module in VHDL have en,shr,shl,load,Din and Dout as ports : entity shifter is port(en:IN bit,Din : IN bit_vector(3 downto 0),load,shr,shl:IN bit;Dout : out bit_vector(3 downto 0)) ; end shifter; architecture arc of shifter...
  8. Y.T_comp

    gates delay in verilog HDL

    I'm sorry about MY English because IT'S not my native language . my question is simply the output X - when input '000'- was 1 so when we change the inputs to '111' we have 20n second of delay ... in this case the X must have the same old statue until 20 nsec finish to take the final statue ...
  9. Y.T_comp

    gates delay in verilog HDL

    just this one why X don't continue in its old state while this 20ns of delay end ?
  10. Y.T_comp

    gates delay in verilog HDL

    I'm so sorry mrflibble i had a wrong in the table i updated to the right one i hop that you can help me .
  11. Y.T_comp

    gates delay in verilog HDL

    hi all :-D i have new question here: i was reading in chapter 2 in mano book "digital design 2'end edition " it was about gates delay in HDL . he explain as normal this paragraph by an example which is : AND have 30ns delay ,OR 20ns and NOT 10ns . and he side that the port X will go to...
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