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Recent content by walkman

  1. W

    saturation issue in video decoder?

    can any one please explain the saturation issue in video decoder? Thanks in advance
  2. W

    why behavioural model of analog circuits are required for functional verification ?

    Thanks for your excellent explanation.if you provide some pdf that would be great help for my thesis . my email id karthik.parigi@gmail.com
  3. W

    why behavioural model of analog circuits are required for functional verification ?

    why behavioral model of analog circuits for functional verification of mixed signal ip?
  4. W

    Digital circuits at high frequency?.......

    Dragonfury, i am taking about core Transmitter/Receiver in HSS ser/des ckts
  5. W

    Can any one expalian ISI in frequncy domain?

    Hi, Can any one explain ISI in frequency domain? Thanks in advnace
  6. W

    URGENT:Real value in VERILOG.... '''''''''''''.?

    Hi, I am doing project in verilog. In my design inputs to one of the module is REAL VALUES .So how to give Real values as inputs.
  7. W

    Digital circuits at high frequency?.......

    Hi, i am currently working on high speed interconnects i want to why we cant operate(use) digital circuits at high frequencies(ex:15Ghz)and why we are going for analog circuits for high frequencies? Thanks in advance.
  8. W

    what is AC Coupling in receiver......?

    Chuckey Thanks for your reply.what is dis advantage if we don't block the D.C? Thanks in advance - - - Updated - - - chuckey In one of paper i had read,he mentioned that "Due to the small coupling capacitance's only the high frequency transitions of the transmitted NRZ data...
  9. W

    what is AC Coupling in receiver......?

    can any one tell me what is ac coupling in receiver ?why we use ac coupling? Thanks in advance
  10. W

    doubt in VHDL.....?uregent..

    Thanks for your reply.. yes it is code for analog modeling not for design just for simulations
  11. W

    doubt in VHDL.....?uregent..

    subtype UREAL is REAL; type UREAL_VECTOR is array (natural range <>) of UREAL; type UREAL_TABLE is array (natural range <> , natural range <>) of REAL; function resolved (S : UREAL_VECTOR) return UREAL; subtype RREAL is resolved UREAL; could you plz any one explain the above lines..i...
  12. W

    could you please any one explain what is PDK(prosess design kits ) in vlsi ?

    could you please any one explain what is PDK(prosess design kits ) in vlsi physical design?
  13. W

    doubt regarding ISI?

    Could any one explain the inter symbol interference with respective frequency of the signal.
  14. W

    could someone help me out in solving this aptitude question

    Suppose 2 persons enter a same room in the morning 5 to 6am. What is the probability that they will enter in 10 min gap
  15. W

    how to deisgn 3:1 mux using one tristate buffer, and ,not gates.

    thank you sir,i have morrisamno but iam unable to find ans...
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