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Recent content by vlsi_design2

  1. V

    Jitter by integrating phase noise

    Hi, 1) I simulated the phase noise of LC VCO at 5GHz in cadence and integrated from fl=10Hz to fh= 2.5GHz to get jitter as follows Jc=1/(2*pi*fc)sqrt(2*integ(10^PN/10) from fl to fh) I find it to be 960ps!! I tried to compare with time average Jc and interated from fl=10Hz to fh=2.5GHz using...
  2. V

    esd protection using a balun

    I am specifically asking about a balun where the single ended port is connected to IC pin and differential port is connected to say gate of NMOS transistors. Any ESD event in the single ended port can give rise to large differential swing at the gates as well which may damage the transistor. But...
  3. V

    esd protection using a balun

    It is believed that a transformer/balun at the input of the LNA provides ESD protection because primary and secondary are isolated. But a sudden esd discharge will propagate as a large AC signal through the balun and may damage the transistors. How does it protect in this situation? Thanks
  4. V

    Noise Figure Measurement of 140 GHz LNA using VNA & Power Source

    Hi, I want to measure the noise figure of 140 GHz CMOS LNA using VNA & power source with probe station. The LNA has 8dB gain and 7.5dB noise figure. Is the measurement error going to be very large due to low gain and high noise figure? I am ok with +/-1dB error. Is there any way to minimise the...
  5. V

    EM simulation with high resistivity substrate in CMOS IC technology

    Hi, Is there a way to account for high resistivity substrate below inductor in EM simulation software? I am designing an inductor in a CMOS process and using high resistivity substrate layer below inductor to get high Q factor. I have momentum and emx software.
  6. V

    Two stage opamp differential feedback with different i/p and o/p common mode

    Hi, I am designing a two stage differential amplifier with different i/p common mode voltage and o/p common mode voltage. When I connect it in closed loop using resistors R2 and R1 , dc current will flow due to difference in common mode. Is it ok for dc current to flow when the amplifier will be...
  7. V

    Black Boxing in Calibre

    Hello, I am trying to pass the lvs of I/O cell available from pdk. There is no schematic but auCdl, aulvs, symbol, hpiceD ans hspiceS models. I am unanble to pass lvs in Calibre and I get the message "source could not be read", no matching .SUBCKT for cell name etc. I tried black boxing using...
  8. V

    GCD fill layer in 28nm technology

    Hi, In addition to active, poly and metal fill layers, do I need to do GCD fill layer for a typical 28nm cmos technology? The kit documents do not clearly explain it. What are the additional fill layers needed a typical 28nm cmos technology?
  9. V

    Simulate odd mode/even mode impedance using 4 port S/Z/ABCD parameters

    Can I use an ideal balun and reduce it to a two port problem and do s param -> ABCD pram and the use sqrt(B/C) to find Zoo. Can I use center tap of the balun to evaluate Zoe?
  10. V

    Simulate odd mode/even mode impedance using 4 port S/Z/ABCD parameters

    Hi, I am designing a coupled line coupler and I want to simulate Zoe and Zoo vs freq. How can I express using S or Z or ABCD parameters?
  11. V

    Check undesired substrate mode...

    Hi, I am designing a CPW transmission line in CMOS at millimeter-wave frequencies (>60 GHz). I dont have any gnd plane shielding but only the substrate at the bottom. There is a chance that substrate mode starts affecting. How to check this in an EM simulation tool if any unwanted mode is...
  12. V

    Cap extraction of an IC PAD

    Hi, I want to extract the capacitance of an IC PAD. Unfortunately there are no pins and I cannot pass lvs and do extraction. I may use a metal res to get a pin out and extract but are there better ways to do this?
  13. V

    Does metal (copper, aluminum) shielding really help inductors in ICs?

    In ICs, the inductors can magnetically couple to the the substrate and cause eddy current to flow which causes power loss (emf^2/Rsub). To minimize this people put metal (copper, aluminum) shielding below the inductor to prevent magnetic lines of from from reaching substrate. Now the catch is...
  14. V

    Basic question on T lines

    Hi, T lines no matter how long they are, if properly terminated with ZL=Z0=R, always presents a resistive load and no capacitive load. Instead if I use a long trace of line of comparable dimension I get a huge capacitor with the substrate (say). Is there an intuitive way to understand this? or...
  15. V

    0.7V ultra low noise supply

    Hi, I want to test an LNA IC. I want to use supply of 0.7V and make it as low noise as possible. I plan to use a 6V lead acid battery and then use a voltage regulator as follows https://www.ti.com/lit/ds/symlink/tps76201.pdf Can anybody suggest better ways? The lab power supplies that I have...
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