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Recent content by viona_s

  1. viona_s

    How to control skew between divided_by and multupl_by clocks of the same master clock and timing challenges with it?

    How to build/balance clock tree for divided_by and multiple_by clocks in such a way it aids timing. Is there any special exceptions needed in such cases?
  2. viona_s

    Close to tape-out few cells are failing IR check by 5% above the 10% limit. On what bases these can be waved?

    If IR drop safe limit for the chip 10%, few cells in one region are showing 15% IR drop means failing by 5%. which reports and criteria need to be checked to wave these violations for tape-out.
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