Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all.
Iam writting system verilog Assertion, i have come across with a problem in below code
$rose (req) |-> ##delay $rose (ack);
in tha above code variable delay i want to be chaging based on contents of some register, but am getting error : delay should be constant ---i tried...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
