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Recent content by Varun124

  1. V

    Separate chains for OCC

    Hi Tony, this is post it mentioned about occ flops in chain. But i was looking is it okay to insert occ flops in any chains are do we need separate chains. If separate chain what is the reason
  2. V

    Separate chains for OCC

    Hi Team, I am working on OCC and i see separate chains are created for OCC is there any reason for such chains. ALso what happens if occ flops sit in some other chain with other flops. Thanks.
  3. V

    How to check if a signal is toggling after some time in simvision TCL command

    Could you please provide some inputs to write an assertions
  4. V

    How to achieve controllability when pin is buss connection

    Hi Team, I was working on TDF coverage analysis i am seeing once scenario. In of the hierarchy all the faults are unable to control and these are coming from buss connection. How ATPG tool detect faults when the controllability is coming from buss connection Thanks in Advance
  5. V

    How to check if a signal is toggling after some time in simvision TCL command

    Hi I was working in simvision environment and I was developing to script to check whether a signal is toggling after some time. Could you please let me know if there are TCL command in the simvision console. I was using waveform values -at time signal but it was displaying one value
  6. V

    Asynchronous scan channels

    Hi Team, I was working on scan compression and all the design have same scan in and scan out channels. What happen if the scan in and scan out are different. If we have different scan in and scan out, then how compression ratio calculated
  7. V

    Coverage Loss on Reset combos

    Hi Team, I have a design and i am using active low reset. To improve coverage i have set this reset to clock. But there are some reset path where top level reset goes to some combos and finally captured to D flip flop. To test the SA1 faults on these combos, the reset should be toggled. The...
  8. V

    Interconnect Delay Vs Clock Period

    Hi Guys, I have one doubt in interconnect delay and clock period. In my design I have a clock source and it reached to an inverter. The interconnect delay b/w inverter output and next nand gate input is more than clock period i.e. interconnect delay = 5.029ns and clock period = 4ns . In this...
  9. V

    Lockup Latches Usage in DFT

    Hi BradtheRad, Sorry when I read through documents, it says we need to add lockup latches for posedge to neg Edge but not other ways and I understood that posedge to negedge it will be same cycle whereas negedge to posedge it will be different cycle. But my question was why we take cycle...
  10. V

    Lockup Latches Usage in DFT

    Hi Guys, I am working on lockup latch in genus tool and when I am adding a negative latch between pos edge clock and neg edge flop to reduce half delay hold violation problem in shift path, why cant we add lockup latch for neg edge to posedge. And we consider shift cycle instead of shift...
  11. V

    Do we need to generate TFT patterns for netlist whose timing is less than Scan frequence?

    Hi All, I have a hypothetical chip whose functional frequency is closed around 100 Mhz and if i am using scan frequence of 200 Mhz, still do we need to generate TFT patterns ?? Thanks in Advance
  12. V

    Difference b/w P1500 and JTAG

    Hi All, I have one doubt regarding jtag and p1500. Jtag and p1500 functionally it do same work. Why we are programming p1500 through jtag while we can use any one of them. Thanks in advance
  13. V

    IO Loopback in DFT testing

    Hi All, Can anyone explain me what is the use I/O loopback in DFT testing. TIA
  14. V

    DFT 1500 IP module testing

    Hi All, I had a doubt in DFT 15000 testing. Let us consider this DFT 1500 is an IP and sits inside a module and this is the master module and it's controls the other module. Is there any integrated test for 1500 ip ( checking the scan connectivity for 1500 register) carried out. If so, can...
  15. V

    How hold violation caused by below mentioned Scenceio

    Hi All In my design D is changing just before clock edge but there were no violation reported. I know it is because of massive hold violation because launch clock is coming early and capture clock is coming because of which data slippage is happening. Can anyone help me what exactly happening...
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