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I still don't understand the question. You can think of SS as a contract between you and the foundry. You should not be getting any chips that perform worse than SS in a mature process. Anything near TT, near FF, or above FF, is icing on the cake. I don't see an immediate need for testing or...
This is one way, with calibredrv. But it is not very intuitive. digital designers want to see the errors in their design environments, like Innovus and ICC. See oratie's aswer above.
I don't know how to help you. If the only information you can give is "it doesn't work", it is of no help. Did you check logs? Did you check folders to see if the gds files were generated? Did you debug at all? Did you try switches at random? Have you tried to run fill on a small design first to...
You can have perfectly correct modules and still make mistakes in top-level connections. LVS would show these mistakes somewhere, not necessarily on the top level when you include everything. Debug debug debug. Consider adding one block at a time if possible.
The process is M9_6X2Z, which means it has 9 metals, the first six are of the type X and the next two are of the type Z. Most likely you are designing with the wrong stack. The most popular stack for TSMC 65 is 6X1Z1U, just so you know, as it is used in MPWs quite often.
In any case, you gotta...
Most likely you are missing some LVS configuration. Try to make a design that contains only a single instance of the SRAM and make that one pass LVS. Then move to a larger design. SRAM's can be tricky for LVS because it struggles with bit arrays and their relative order. Say, it tries to match...
scripting is usually the way to go. declare a variable x and a variable x_offset. drop the stripes one by one, add x_offset to x, rinse and repeat. add some corner cases in the form of
if (x near macro) then skip
if (x near macro) then apply offset times 2
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