Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I know the potentials of Embedded Linux. I am VHDL designer and I have seen people using Petalinux with Xilinx FPGA.
I always had some questions regarding Embedded Linux. But first let me tell you what I know about it.
Yocto was made into Petalinux by Xilinx. It runs on Zynq(I don't know...
I am trying to simulate a sensor input into my VHDL design. Now I need a component within the testbench that mimics that sensor. I am thinking about asking the manufacturer of the sensor to provide some sort of simulation model for that sensor so that I may use it in my VHDL testbench.
What is...
Hi all,
Just wanted to know whether there exists any certification for verification engineers as well? Like there exists certifications for software test engineers like ISTQB. Please note that I am verification engineer and I use systemverilog for verification.
Thanks and regards.
Hello guys,
I adopted the following procedure to install Linux on Windows
How to enable Linux on Windows .
I have installed modelsim 2020.1 on my windows machine. I want to run commands like vlib and vcom on the Linux shell that I have enabled using some options within Windows(procedure...
Hi,
I am given a systemverilog design. My task is to optimize (reduce) the size of the design in terms of FPGA synthesis, and I need to increase the speed of Design. The target FPGA is Xilinx Artix and IDE is Vivado.
I want to know:
1) What may be the programming approaches i.e. what things I...
Hi,
I am an engineer working in VLSI industry. I want to switch my job, but the job requirements also enlist the PERL scripting capability for verification.
So is there any good tutorial that shows how that automation works? Like If I wrote a module and test bench in Modelsim, and I want to...
Hi all,
I am working on Project where I will design an FPGA based data process accelerator. For that purpose I need to connect that FPGA (Xilinx V5 - evaluation board) to a PC with Ethernet port.
Now there few problems which needed to be addressed.
1) If I load full UDP/IP stack in FPGA then it...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.