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Recent content by srp8514

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    Query on Latch/ICG timing

    HI, 1. Time borrowing needs to be enabled by the user .libs have no information about time borrowing. The tool understands the a latch based design and if time borrowing is enabled then it will optimize the design accordingly depending on the combo logic between the two latches 2. Yes time...
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    interview question on gate sizing

    @Yanxiang You might have seen a reduction in dynamic power. Dynamic power = 0.5 * C * V^2 * F * (activity factor) By reducing the gate size you are reducing the pin Cap. Which could account for reducing the dynamic power.
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    VLSI design project ideas for final year

    Hi, Go to https://opencores.org/ and pickup some good ideas from there. It also depends on what you want to exactly do : 1. If you want to stick with RTL design : Implement a core from opencores. Try to synthesis and perform PNR Read about the issue queue for out of...
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    What are the issues faced when transition violation occurs?

    Usually in a design the STA recipe will set constraints for transition time for data and clock nets. If the any violate the requirements the toll will report a transition time violation. Usually you need tight transition time for better performance and power. If you have bad transition time...
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    Robust clock tree design

    Hello, If you are given design whoes clock root is a ICG and end points are 1000 flops. What clock style is better a clock tree built using ICG's only or buffer/INV only and why ? srp8514
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    interview question on gate sizing

    Usually the P/N ratios are changed to modify the pull up or pull down strength for the cell. In you case since the PMOS is being made weak that means there was a requirement for strong NMOS meaning cells having better 1->0 transition. These type of modifications to P/N ratio are very common...
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    what are the steps for building good and robust clock tree.

    This is a very generic and a wide question. Most of the time once you have completed the initial placement, then based the following the cts tool will build a good robust clock tree 1. design constraints (SDC) This will contain the basic clock definations, false_paths, multi-cycle...
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    Flop to Integrated clock gater timing issues

    Hello, If you have a flop that drivers another flop and a integrated clock gater (ICG) then which path will be critical ? The Flop to ICG or Flop to flop ? This was an interview question. Thanks srp8514

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