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Hi Dave,
I referred to **broken link removed** thread.....
may be my understanding is not enough but let me ask you one of my basic doubt ........see you have virtual/abstract class UART_BFM in UART_pkg and one virtual method in it setNbits().....and then in its child class U_TX you define...
Re: Sequence in system verilog
## is a notation used for timing delays............ ##1 means after 1 clock cycle ..............regarding sequences you make sequences and then use them one by one with some conditions in your assertions(via property)......in assertions we are verifying a sequence...
your question is not clear ............anyways you want to basically develop a testbench and drive your module at every posedge so you basically has a DUT(design module) then create a interface for connecting your TB to your DUT and then make generator class or module in your testbench and then...
in code1 print() task of base class will run or execute ..............in code2 print() task of class derived will execute.......you can refer to www.testbench.in and refer to inheritance section of oops
Why we need Abstract class in our Testbench.........what is advantage of using it.......normally in its child class we declare the functions or tasks with full functionality then why to create a abstract class???
In testbench we always use new constructor in classes as:
function new(string name, vmm_object parent=null);
super.new (parent,name);
endfunction
Be it VMM,UVM or OVM it is used everywhere ........could anyone explain this line by line and why we need to use this????
I am 2 + experience as a front-end Design & verification Engineer. worked in soc level and ip level verification both(various ip like CRC,Timer etc., security protocols AES, audio codec g722 etc). I am looking for a job.............but now a days recruiters are asking for special expertise like...
hey thank you ...i read out the paper i.e. how approach to verification enhanced from traditional approach regarding the interconnection between design and test bench..i will try and follow ur advice ......currently i am doing designing in a project .......vl try to co-relate the things together...
why we define clocking block normally in interface in a test bench???? is there any significance of this??
and one more thing that if we do not define any clocking block in a test bench then also it works fine how???? is there any default input skews and output sync time ???
My code goes like this:
fork
begin
....
forever
begin
process 1;
if (some condition)
break;
end
.....
end
join_none
My doubt is if that "some condition" is met then will break will help to come out of forever block and fork-join_none block...
Thanku vrymuch ........it really worked out for me ..................but there z one question that if we can give seed to std::randomize(variable) ? and if yes then how can we pass seed value for randomization into this ?
how to create and write a radom variable in that particular created file?
i use file which is integer type
then file=$fopen(path where i want file to be created)
then $fwrite(file , random variable)
then $fclose(file)
but it is not created and working
plz HELP
i need to write a task which generates random binary data and write it in to a file? can anyone help me because i can not use randomize() method and rand longint because they can not be used without class declaration and my task is not under any class?
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