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Thank you for the fast reply. I pulled up the DRC deck and am looking through it.
Are those key words to look for?
1714774983
I found these lines within DRC that are used to define the chip, I believe. ChipWindowUsed is not currently defined.
There is list of EXTENT layers that get mapped to...
I am urgently trying to resolve some drc errors for a tsmcN65 process.
The errors are related to enclosure such as DM1.EN.1 with rule defined as:
DM1.EN.1 { @ Enclosure by chip edge >= 2.51 um
DUM1 NOT (SIZE CHIP_CHAMFERED BY -DM1_EN_1)
}
The area is defined by Pr Boundary layer. The...
Thank you. That was the conclusion I was reaching. The violations are on the sealring itself. I even tried wrapping the top-level design in sealring with same errors.
I put a TSMC provided seal ring around a design which passes DRC but when I tile the design with the seal ring for the top level, I end up with 5 errors related to the seal ring. Any ideas on how to correct?
RV.W.1.WB
RV.S.3.1.WB
...
The check text for one
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