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Thank you for your answer but let me clear few things:
1) We are not talking about connecting drain of NLDMOS to power net rather we are talking to whether connect HVBN (which is an isolation layer of HV devices) to the drain of NLDMOS or to power net. By default every NLDMOS has HVBN layer and...
I am facing some issue regarding ERC. i have design a layout of inverter using SMIC 180nmBCD PDK,. i have used high voltage device NLDMOS (nld40h_ckt and pld40h_ckt)
and i got an ERC error mentioned below.
There is NWHT i.e. HVBN layer associated with aforementioned transistor which is basically...
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