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Hello all,
While doing EM for power rails in Totem, they will represent the target to be achieved in percentage (for ex: 400% at 125c, 1v). What does it represents exactly???
As per i know the standard routing pitch is required for
i) All the pins placement on the intersection points, so that the P&R tool finds this pins and routes over this routing pitch.
ii) Helps to avoid DRC errors (since by using via-to-via pitch distance for pitch spacing).
Q1) Is there any...
Hello all,
I am doing the layout of Power supply PAD for VDDPST supply (I have 2 supplies VDD and VDDPST of 1.8v and 3.2v). This PAD is used to supply power to the IO's. For this i have used N-type diodes and one MOSCAP (NMOS cap) as shown in the screenshot. As per my understand,
#...
Hello all,
I am doing the layout of Power supply PAD for VDDPST supply (I have 2 supplies VDD and VDDPST of 1.8v and 3.2v). This PAD is used to supply power to the IO's. For this i have used N-type diodes and one MOSCAP (NMOS cap) as shown in the screenshot. As per my understand,
#...
Hi penghan,
i have done the post layout simulation using the HSPICE by using the following command to invoke the HSPICE.
hspice -i input_netlist -x extracted_RCfile
But i observed not much variations in the output signals. Is this correct?
Hello friends,
I have created a layout in Virtuoso, extracted RC for the same using StarRC XT. Now i want to do Post layout simulation using HSPICE. The RC extracted netlist contains R and C values for the different nets, now how can i interact these RC values with the .SP netlist i have and...
I have created a list for box creation and trying to access the lower left coordinates but it is showing as "range" as shown below. What is the problem could you explain me.
a=list(1:2 3:4)
b=car(a) ;gives (1:2)
x=xCoord(b) ; showing as "range"
y=yCoord(b) ; giving 1
Thanking you,
santhosh
pspice power calculation
What is syntax for calculation of different power components such as avg, leakage and dynamic using Spice??
Thanx in advance!
santhosh
why height fixed in stanadard cell
Hi, could you explain, how the height of a standard cell is fixed while developing a std. cell library. Is it height of a tallest cell, then which cell they will consider as tallest cell in a library??
How much should be the width of std. cell? Generally it...
layout guidelines for 45nm
What are guidelines provided to draw the layout (for Digital blocks like Standard cell or memory) in 65nm and 45nm Technology.
Thanks & regards,
santhosh
Hi, add these guidelines also
1. Avoid power connections of the transistors connecting with guard rings. Use power tapings instead of that.
2. Increase the metal connection widths where ever it si possible. It gives good RC values.
regards,
santhosh
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