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Actually i create register file memory and data memory for my simple processor that's why they have so many there. You can look at my code below.
///////ALU
module ALU (
input [31:0] A,B,
input[3:0] alu_control,
output reg [31:0] alu_result,
output reg zero_flag
);
always...
WHEN I COMPARING MY GOLDEN.V WITH revised netlist during conformal , I got these non-equivalent point for every reg memory and for every data memory. I don't know what to do with these non-equivalent point. I've been stuck here for the past four days. Please help me in this and how...
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