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which camera are you using?
and how you are converting the data digital, is it an external adc or inbuilt with camera?
the question you are asking is inappropriate, pls include some detail of components you are using, and what are you trying to do, then only someone can help..
i don't think you...
use of dcm was tough but useful only to some extent
however i did not find an accurate method to make clock of any order
i lost the error message now sorry for that
1. clock divider by use of counter is most easy method and useful, as most devices provide a range for operation e.g. from 7Mhz to...
problem solved
Digilent virtex-5 board with VMOD CAM is best option
it works in real time even on colour images
http://www.digilentinc.com/Products/Detail.cfm?Prod=GENESYS
Re: Image processing on fpga
problem solved
camera can be any
FPGA can be any probably greater series than spartan-3, however i have not tested on spartan-3, but tested on virtex-5
the thing is that an external ram is required to store the large amount of video data to do some image process of...
the problem solved
actually just after the transmit stage i was sending the power down stage
so after initializing the lcd we need to stay in transmit stage
rest everything is correct i made it run
see the video below:
https://www.youtube.com/watch?v=wfOOsut469Y
1. If you want to use 5V battery then simply check the voltage of the battery to be 5v using multimeter.
2. Usually, you will get a 9V battery from market. use that battery and after this connect an 7805 IC to regulate it to 5V.
but don't forget to use a voltage regulator 7805 in either case...
see this video
http://www.youtube.com/watch?v=wfOOsut469Y
study the datasheet of vmod tft
**broken link removed**
code is easy you can do it
ask for doubts not code
if you need code reference code is also provided on digilent site
today i checked the PCLK, HREF and VSYNC signal on MSO. These signal are output by camera.
Vsync signal comes out to be 50 Hz
Href signal comes out to be 14.46 KHz
PCLK signal comes out to be nearly 16 KHz
i think this to be wrong as PCLK signal is expected to be 8.86 MHz by default, as per...
1. I am using system clock as "CLK" ,and detecting PCLK,HREF,VSYNC signals using edge detector circuit as you told (see entity top, there i created process for detecting rising, falling edge). After this i need to use the edge of HREF,VSYNC to know when pixel data is valid, that is why i used...
the above code i posted is the full code of my project out of which i am unable to form the image
while rest of the code is working i.e. LCD,STEPPER and TFT is working except the camera.
however camera does give pixel output on led's and tft screen(image i posted before) and on lcd the number of...
thanks
that really explained clearly the two methods
i am posting my full code here you can check here
ask if you don't understand anything
----------------------------------------------------------------------------------------------------
-------------this is the top...
thanks that was helpful
i used edge detector instead of setting clock_dedicated_route=false
and the code synthesized
but still picture is not formed...
i don't find any difference in signal'event and setting clock_dedicated_route=false
or by using edge detector
make a block ram and prestore it with image data
then transmit to any display device
see my following video
https://www.youtube.com/watch?v=wfOOsut469Y
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