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Recent content by ricl

  1. R

    vhdl assertion question

    I have this assertion statement: ... begin assert (data_out = expect); report "data mismatch" severity error; ... my understanding is, only when data_out not equal to expect, the message "data mismatch" will display I checked that data_out and expect are same, but I always see this...
  2. R

    Anyone know how to dump waveform in VCS, Design is in VHDL?

    Any one know how to dump waveform in VCS , Design is in VHDL ? your reply is highly appreciated!!

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