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hi frnds
im having one doubt im using a two port dpram from altera megawizard where in my wrside data is 8bits wide and rd side i need 48bits but its not giving the desired data to me wt i need to do is there any solution plz let me know thnks in advance wt ever the AW may be
Thank you for your valuable ans sir one more question
im getting a signal whose on period is 10 microseconds and off period is 50 microseconds and another signal is inverted to it i mean off period is 10 microseconds and on period is 50 microseconds with the clock of 16.25Mhz, by comparing both...
here is the code for which i have written sir once u check out
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity vsync is
port (
clk : in std_logic;
vsync_out : out std_logic
);
end vsync;
architecture rtl of vsync is
signal rst...
Hello Sir, firstly im very thank ful for responding to my question, im sorry for not giving the complete info regarding the signal generation.
here are my specifications one signal is generating at 60hz that is ON period of that signal is 5 micro seconds and OFF period is 11 micro seconds, with...
Hi Frnds of Great Brains im new to this vlsi world i need one help from you
my specifications are as below
one signal is generating at 60hz rate wt 65Mhz as clock as reference from that i need to generate 120hz rate how do i proceed i will be very much thank ful if the code is presented in...
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