Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by putturvenkatesh

  1. P

    can any tell about well proximity effect

    http://www-ise2.ist.osaka-u.ac.jp/~hasimoto/pman2/data/pdf/92.pdf
  2. P

    Layout Optimization Technique

    This is a very generic question. Can you give some details on which layout you are working on?
  3. P

    Layout extraction

    It is difficult to understand. Can you please explain the requirement?
  4. P

    challenges in lower technologies

    Common challenges are: 1. LOD 2. WPE 3. DFM 4. Diffusion proximity effects 5. Optical proximity correction related rules 6. DIBL 7. Hot electron effect etc.. For each topic you will get materials if you search in Google. Let me know if you need any help with searching. Regards, Venky
  5. P

    Integerator Reset Circuit

    The resistor is required to discharge the capacitor. Though you will not find much about your question, following may help with integrator and low pass filters. https://www.edaboard.com/threads/132921/ Regards, Venky
  6. P

    layout post simulation and the schematic simulation is different

    The action depends on design! What exactly do you mean by eff? Find out what in layout capacitance is affecting the performance. This may be some particular node having more capacitance or between two nodes there is large cap, which circuit is not able to drive. In such cases, either route such...
  7. P

    Debug naming error in Calibre LVS

    There may be a connection error. Is this the only error? Can you attach the entire error report? And if possible, layout and schematic snapshots?
  8. P

    Digital signal transmission through antenna

    Digital signals are two levels of voltages. Where as to transmit through antenna, you need something which is continuously changing. Look for a book with antenna theory basics. You will get answer for your question.
  9. P

    Regarding tapeout using cadence- help neede urgent.

    Tape out is procedure to send for fabrication. This is very costly for an individual to go for. Check if your College has some tie-up with umc fab. Then talk to your prof and get some silicon area booked in the next test chip.
  10. P

    Analog VLSI design training/courses in India

    There is a 2 weeks training program by ekLakshya VLSI R&D Centre, Hubli starting on Jan 3rd, 2011. Let me know if you are interested. Curriculum : Basics of RLCVI -- expectation of core companies Regards, Venky

Part and Inventory Search

Back
Top