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It is paramount to remove any DC offset in the incoming signal. Usually, it has to be digitally filtered by a DC- blocker or some other algorithm. The simple one is to calculate a sum of all incoming data, and subtract +/-1 from the signal if the sum was positive/negative. It is very slow, but...
I believe that by two 0-iterations assumed bringing any angle from 0-360deg into 0-90deg sector, based on sine syandard simmetry properties:
sine(-x)=-sine(x) and
sine(90-x)=sine(x).
So using two steps one can converf any angle into 0-90deg sector and then proceed with CORDIC iterations.
Apparently, you have found few methods of calculating the phase offset. Theoretically, they all should give same accuracy limited only by acquisition S/N, and number of samples and effective bandwidth.
Before diving into uC check if any jobs available in your area/country. Most of small uC jobs has moved to Asia, in US job market requirement is large FPGA/SoCs (mostly military, citizenship and clearance required). All uC skills are hard linked to the hardware silicon, so your knowledge of PICs...
This is one possible solution using PSoC5 micro:
Phase offset and Quadrature signal generator for lock-in
The demo project shows generation of phase-shifted output signal for arbitrary phase. The project uses digital Counter to measure period of the input clock and to generate a phase-shifted...
The trapezoidal generator is written in Verilog, and consists of two DDS generators: one to control output frequency (duration), and another to control ramp frequency (risetime). The output bus is driving 4-bit R2R DAC, which output amplitude is controlled by the driving voltage V_analog. Code...
You can find example of the PSoC5 trapezoidal signal generator here:
Trapezoid generator with adjustable rise/fall/amplitude/frequency up to 1MHz?
YouTube demo:
Actually, I am thinking of sequential combo PWM-DDS, e.g. PWM feeding the sampling clock of DDS. If for PWM dF/F ~ F, and for DDS dF/F ~ 1/F, then overall precision of the system will be
dF/F ~ F * (1/F) = const. Question is how to divide frequency between PWM and DDS optimal way.
KlausST,
Thank you for reply.
Exactly, to have dF/F = const, dF has to be proportional to F.
From the feedback I get feeling that there is no established solution, which may justify developing my own. I have no application in mind, this is just "theoretical" exercise which I want implement...
KlausST,
I have DDS programmed into FPGA, but was quite disappointed that it's relative accuracy drops at low frequencies as ~const/F. You have to add ~8bit on top of high frequency range to avoid phase jitter, which brings 24 bits you have calculated to 32 bits.
Again, my question is rather...
c_mitra,
Thank you for reply, it kinda reminded me the the old days, when I was actually doing ESR and NMR work. Now I am a hobbyist trying to understand how uC works and how to produce with it accurate tones with same precision over the large span. Some keywords may be helpful to stirr me in...
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