Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a doubt that, whether we should add the calculations of how to get output (y) in the testbench also???
When added that calculations again in the testbench i am getting the output... but wen i removing that calculations am not getting the output.. am getting the initialized...
Fixed point package in vhdl
Hi
i am using Actel libero 9.0.0.15 version. I have to use sfixed or ufixed types to represent some of my coefficients of filter like 0.0125, -0.125, 3.125 etc. But the problem is that while i am using this type error is showing while compiling the hdl file. the...
Hi all,
I am new to vhdl. I want to give -0.01277 to a generic b0(assume). I gave it as generic( b0 : sfixed(16 downto -12)),
and in generic map (b0 <= "-0.01277"). But while compiling it is shown as sfixed is not declared(vhdl-1241 error).
What should i do to resolve this issue. Can anyone...
Hi all
In vhdl coding, i have used sfixed(16 downto -12) type.
but while compiling it is shown that sfixed is not declared.
Can anyone plz help me to resolve this problem.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.