Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dummy generation
It is easier to use the cadence virtuso tool to generate the dummy layers in the empty area, but if the empty filed is too complex, you have to edit it manully.
Adding a library
what does 'THJA104K035R " mean ?
usually inside your process file, there is ff, ss,tt,fs,sf. u had better refere to all the above 5 instead of "THJA104K035R "
non-epitaxial wafer
if I remembered correct, the EPI wafer is more expensive, while it will have better performance than the non-epi wafer in some fields, such as preventing latch up
Added after 8 seconds:
if I remembered correct, the EPI wafer is more expensive, while it will have better...
Nonvolatile memory
for this design area, the main difference is caused by the reliabilty.
some changes are specially used for the reliabilty, and there might be some test modes developed for flash specified reliability.
even for the algorithm. my understanding is still for realibilty...
export cadence to gdsii
This is the right way.
and inside the popup window, you can use a file to define which layers need to stream out, and what does not need. because sometimes you do not need to export the flag layer.
of course you can.
if there is no requirement for the performance, you only need to draw the phsical connection.
you can refer to the layout of NAND2 in most of the textbook.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
