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Hi Sharif,
Hold time should be less than the combi delay between the flops...Its not the other way round!!
@pradeep..
Hold check is done one edge prior to the capture edge.
Now if ur clock A has 10ns time period so its edges are 0 10 20 30 40
clock B also at 10ns but fall...
Hi Sharif,
For a CMOS configuration, the source of Pmos and Nmos should be connected to power and gnd respectively. This is when you are talking of one Pmos and One Nmos transistor as is the case in an Inverter.
But when you have multiple transistors as in the case of a 2 i/p Nand Gate where...
Hi Ravi,
You can refer to a xilinx document "Divide by Odd circuits"
But before that why dont you try yourself as RCA suggested... you might surprise yourself:wink:
cheers,
Hi Sharif,
Constant propagation helps your tool to reduce the runtime and avoid false violations during timing analysis...for eg your reset/enable signal which which will be held at constant value in a particular mode should not be analyzed for all the cases...when you know that particular...
@vivek_p,
IN the pdf
"Tc_jitter=0, Tc_skew>0
The minimum clock period increases. The maximum
hold time increases ..hold time condition easier to
meet"
we all know that positive skew helps in meeting setup violations and makes it harder to meet hold requirements...
Maybe its a working copy...
Hi Vid,
Top-down compile, in which the top-level design and all its subdesigns are compiled together
--low memory footprint designs, use ILMs if design is memory limited, interblock dependencies are resolved by the tool,
Bottom-up compile, in which the individual subdesigns are compiled...
Hi Abu,
EDA board is about discussing things which you feel difficult to comprehend, you can request how to draw a cmos schematic but not ask someone to finish your home work.
You stand a chance of getting a warning from the forum moderators if you do so.
I would suggest you to go through...
Re: dubts regarding back end flow
Hi Sharif,
TDF is Top design format which consists of pad information for the design.
Port is through which the design communicates with the external environment whereas pad is one where you can include ESD circuit along with other electrical safeguards in...
Hi ASIC_int,
group_path -name inputs/outputs/combo -from/to [all_inputs]/[all_outputs]
the R-R path is in clock path by default so this way you can divide it inputs/outputs/combo/clock so that each path group gets optimised independently and one Worst violator in one group do not block the...
Hi ASIC_int,
group_path is effective as you can separate R-R paths from I-r,R-I and I-O paths...If you do not separately group these and you have a worst path as I-O path the tool does not optimise the other remaining violating paths as it aims to reduce WNS rather than TNS..so even when there...
Hi Falcon,
Use wild card entry as lostinxlation suggested...but using wildcard entries can sometime lead to performance hit...So do prefer the second option and remove for the cells you need.
cheers,
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