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Recent content by pankajpc

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    Separation in non overlapping clock

    Hi Fellas, I had a question regarding non overlapping clock. How do you decide the separation between non overlapping clock for negative charge pump design for cmos image sensor pixel transfer gate. The separation between the clocks can be 1ns, 2ns, 5ns etc. How do you fix the separation for...
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    Regarding circuit design

    by standard design techniques, I mean putting all the transistors in saturation and designing the opamp.
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    Regarding circuit design

    gm/Id by boser please refer to the same. 1655917854 you can use gm/id by boser or you can use the standard design techniques. but sometimes gm/id is recommended.
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    [SOLVED] how to delete simulation files in cadence 55nm to free space

    you have to go to your home directory and delete .tran files if you are doing transient. 1648124098 Also, you can go to options and select selected nodes instead of publishing all the node voltages and currents.
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    MOS switches in FeedForward Equalizer (FFE) for SERDES for 112GBPS

    Hi All, I was wondering as to how to design CMOS switches for FFE for SERDES in 112GBPS. It is a quarter rate architecture. I am using PRBS data pattern but the switch is showing more output at sampling node (Node after sampling switch. where the sampling capacitor is put) then at the output...
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    MATLAB CODE FOR CDR & PLL and also jitter modelling

    Hi, Any idea about Matlab modelling for PLL. What are the factors/ things we have to consider. Can someone give me a starting point as to some document or code that I can start with. thanks
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    MATLAB CODE FOR TX & RX SERDES JITTER BUDGETING FOR CDR & PLL

    1. Would you know of any method or technique for jitter budgeting for PLL in Tx and PLL & CDR in Rx from point of view of circuit design.The RX PLL & CDR Specs should also include the clock tree. 2. THE ABOVE MENTIONED REQUEEST HAS TO BE PERFORMED THROUGH A MATLAB CODE.
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    PLL & CDR in Serdes 28Gbps NRZ

    My questions are as follows:: 1. What kind of CDR to be used for 28GBPs Serdes receiver. From my own research i found out that there are 3 to 4 different options available and i am not sure which would be used. 2. Would you know of any method or technique for jitter budgeting for PLL in Tx...
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    Calculation of random jitter fom phase noise of vco in PLL

    I have a 16GHZ pll and div by N is 160. I am trying to calculate random jitter from phase noise of VCO. I TRIED IN CADENCE by setting noise source type as jitter and then selecting FM jitter or PM jitter. I was wondering how to plot jitter information using above choices I have made in direct...
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    RMS JITTER IN Phase locked loop

    I am trying to calculate rms jitter for PLL. Will abs_jitter command in cadence calculator after selecting the clock suffice. The result, I get is absolute jitter. Is it the same as rms Jitter. please advise regards -pc
  11. P

    PLL (phase locked loop) loop bandwidth

    So what you mean is to give a sine wave at the reference input and look at the vco o/p. Actually, two pole pll does not depend on damping, however 3d order PLL because of smoothing capacitor C2 is actually 3 pole system which is dependent on damping. Can you please walk me through the test...
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    PLL (phase locked loop) loop bandwidth

    if one wants to measure pll loop bandwidth of type 2 PLL in spice how do i do that. Actually, the LPF has a R1 and C1 and another smoothing capacitor C2 , 1/10th of C1. Typically, because of C2, R1, C1 and VCO we will have 3 poles and a zero.
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    PLL deadzone measurement

    thanks for your help. I figured out lpf and vco. I was wondering if i want to calculate pll loop bandwidth in cadence, how do i do that. it is a type 2 pLL with C2 1/10th the C1.(ACTUALLY A 3 POLE SYSTEM BUT ITS EFFECT IS REDUCED BY USING A SMALL (1/10TH) VALUE FOR c2)
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    PLL deadzone measurement

    Thanks for your help. rgds -pankaj Hi, I was wondering f if you have any references to understand PLL more clearly. The cadence schematic is not clear and difficult to read in your application note. Can you refer me to application note or book or IEEE paper which will cover testbenches in...
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    PLL deadzone measurement

    Can you please help me with PLL deadzone measurement in Cadence/spice. I want the testbench for the same thanks -pc
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