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Analog Layout. If you want to go slow, there is the Book "Art of Analog Layout" by Alan Hastings.
For something faster, can you give information about which process node, foundry, what type of design (slow/fast, precision, timing, high speed, RF, etc) you want to implement? That might help...
This is like saying, I know how to drive and repair a car, but can I get some material on how to drive and repair a train.
This is such a large subject and unless you specify some sub-topics, how can someone help? You want practical examples. But you have not specified of what. Digital Design...
What do you mean by the above? Which values are not being observed?
What does the above sentence mean?
Are the transistors biased properly?
Have you set the Gm correctly?
Is this a fully differential amplifier? Do you have CMFB?
Show your circuit so we know what is going on.
What you seem to be measuring is your closed loop gain. Which is this case is 2 or 20log(2)=6dB.
In your testbench for measuring the gain, you have not broken the loop.
You have a PMOS input comparator. And a supply, VDD = 0.8V.
Now with input at 0.751V and 0.749V, your PMOS devices M1, M2, M7 and Mb are all dead. How do you expect your comparator to work with such inputs?
With the inputs at 1.2V and 0..3V, still one half your comparator is still dead. The...
Basically in the 0 current situation, you want the positive feedback to be strong. For that you are keeping the current mirror ratio for both PMOS and NMOS >1.
While this should always work, there is the situation of true 0 current. Where still 0 x Large Mirror Ratio = 0. So in theory you would...
One thing you would want to check is how your PVT corners are defined.
With your PTAT bias version, your frequency is a function of 1/(R x C x Vth)
In your process corner file, can you independently vary R, C and Mos corners?
Also, I am guessing here with the limited info, in the LDO version...
Your zero current state depends on a bunch of things to happen together.
Vds mismatch in the PMOS Mirrors will cause the currents to be different by default, causing positive feedback to be stronger.
Vth mismatch in the NMOS Mirrors due to different Vsb will also cause the currents to be...
I am not sure what you mean "without VSS" I am guessing a negative VSS.
But any way, as you would have been taught, the critical specification for this would be Input Common Mode Range.
What is the range of inputs your OPAMP can expect to work with? Is it Rail to Rail (0 to VDD) or more...
1. Back calculate the Open Loop Gain and Bandwidth Specification.
2. Also check the Input and Output Common mode Range. (Rail to Rail input/output or anything else.
From 2 you can decide whether you need NMOS input or PMOS input or both(rail to rail)
From 2 you can also figure out whether you...
I "think" fundamentally you are trying to apply KCL/KVL type DC equations to a system which has loops.
When there are loops, we have to look at causality. And a system which is has right half plane poles will be non-causal.
By my understanding we cannot apply regular DC equations here.
( We can...
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