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Recent content by N vijay kumar

  1. N

    hi every one any one tell about $readmem

    I am intrested in receiving data from a file to code, can any one tell in detail about $readmem, its syntax and its functionality in detail.
  2. N

    Doubt in C programming

    ohhh sorry for my mis understanding...... thank you Alex.....
  3. N

    Doubt in C programming

    yes, we can declare some variables as volatile which are most accessed in the code .... for example in a for loop we can declare the count variable as volatile........ volatile variables are fast to access by the compiler as they are directly available as other are from...
  4. N

    any one give detail view of sc_process_handel and sc_spawn

    my doubt is sc_process_handel a1= sc_spawn(); sc_process_handel a2= sc_spawn(); wait(a1.terminated_event() | a2.terminated_event()); i have to stop or kill or terminate one of these sc_spawns so is there any one to help me..........
  5. N

    any one give detail view of sc_process_handel and sc_spawn

    can any one tell in detail about sc_process_handel and sc_spawn. why and how they are used. and how can we terminate a spawned process or thread.
  6. N

    diff between verilog and VHDL

    thank u, i think verilog is so simple and easy to understand.
  7. N

    Need Help on combining two processes in VHDL

    dont mension state in sensitivity list when LowState => temp <= "0000"; if(pulse = '1') then temp <= count;//i dont under stud wy u used this temp regisrter count <= "0000";// when pulse is present then counter to be counted => count=> count+1; state <=...
  8. N

    diff between verilog and VHDL

    hi, i dont know how we write code in VHDL. can any one give code for a single task in both VHDL and verilog so that i can easily understand from that. and i can also get the similarities and differences in coding between them.
  9. N

    diff between verilog and VHDL

    """" Verilog lacks the library management of software programming languages. This means that Verilog will not allow programmers to put needed modules in separate files that are called during compilation."""" i dint get that, as we can write modules in separate...
  10. N

    diff between verilog and VHDL

    hi every one, I have a doubt that chasing me from my first class of verilog, i.e, what is diff between verilog and VHDL.is both are difference in total method or the difference is only syntaxes. i want to know the strengths and -ve of both of them...
  11. N

    the meaning of this verilog code

    hi, "{}" this is a concatenating operator in verilog. hear {1'b0, fifo_rddata[15:11], fifo_rddata[7:0], 2'b00} means we are forming a 16 bit register with 1 bit by 1'b0...
  12. N

    Need Help on combining two processes in VHDL

    hi, begin always@(posedge clk) begin if(reset) count<=4'b0000; presentstate<=LOW; else presentstate<=nextstate; count<=cnt; end...
  13. N

    Writing simple test bench

    hi morabian, can u plz give the way u tryed to compile it that is the command u used ........... in the command u have to specify both the files that is the latch.v and test_latch.v >>>> irun latch.v test_latch.v <options> if the two files are not in the directory u r...
  14. N

    can any one tell in detail about arm processer in detail

    can any one tell in detail about arm processer in detail from basics ......... as i am new to this group and as well as new to arm...........
  15. N

    Instantiation problem

    let your top module has input m and out put n....... let say x and y be your two modules. x(a,b); y(p,q); let say inputs a,p; outputs b,q; then //instantiation x mod1(.a(a1),.b(b1)); y mod2(.p(p1),.q(q1)); then a1=m; //top module input to first module p1=b1; //as out put of...
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