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Hi Prashanthanilm,
Sorry for the dealyed response, the back ground for my question was scan sticking that is used for testing sequential circuits.
One of the considerations while doing an LSSD or a mux based scan is that if the clock to out delay increases equally everywhere in the circuit...
Hey,
I had a query with regard to delay in a Flip Flop.
Does increasing my clock to out delay affect my input to output delay in a D Master-Slave Flip flop?
Thanks,
muchagracios!
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