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Hello,
I have a question about the following self-bias circuit:
In the above circuit, m15-18 represents the start-up circuit.
How do these transistors help to start up the self-bias circuit?
what is their effect?
where does the current m15 and m16 go?
can you explain the general...
Hello,
I want to measure the phase margin for a two-stage amplifier. I wish to adjust compensation capacitor using tuning tool in ADS and then measure phase margin from magnitude and phase graph. But, the problem I face is that every time I change compensation capacitor value, 0dB-crossing point...
I have used a structure including 109 Receivers and 4 transmitters in order to do MMW imaging(multistatic imaging). Imaging was done in 3 different frequencies. So, now I have electrical field in each direction at each receiver point resulted from each transmitter at those frequencies. I just...
You know I want to use this integrator in my dual slope ADC. so, I should solve this problem in a way. I want negative lead to be constant. Is there any solution?
Hello,
here is my circuit which is implementing negative feedback. the input is just a sine wave with DC level of 300m V and amplitude of 200m V:
our opamp is ideal. But when I simulate it, opamp negative lead represents the following plot:
it is weird. why? I expect ot to be constant all...
Here is the link to this flip flop:
https://www.engineersgarage.com/vhdl-tutorial-17-design-a-jk-flip-flop-with-preset-and-clear-using-vhdl/
I just used this
Hello,
I have created a flip-flop using the following structure:
it is my flip-flop testbench circuit:
I have simulated this circuit and here is output result:
it seems it wants to change, but it can not. what is the problem do you think?
I have tested Nand3 lonely in schematic and it...
thank you for your answer. I think by "initial condition", you mean initial voltage for capacitor ,which I put it equal to zero. But output seems weird. here is my circuit:
output voltage would be like this:
voltage of "common" node is like this:
both of voltages are weird. "common" node...
Hello,
part of ADC is a Sample&Hold circuit. here is the circuit of my simple S&H circuit:
its symbol in the original circuit is shown in the following:
input signal is a 33KHz 200m volt sinusoidal wave with DC level of 300m V. sampling frequency is about 4 times of input frequency. it is...
well, because opamp is in a negative feedback loop, I expect output to go from 900m to 1.2 volt, with constant current (or with a constant slope line).
Hello,
I have designed an integrator as in the following:
but I do not know why in my simulation, output is like this:
output is saturated at 1.2 v (supply voltage).
I have adjusted ideal switch parameters in cadence virtuoso as shown below:
my circuit is shown below:
V7 and V6 are 1.2 v DC voltage source. finally the voltage between R1 and switch is shown below:
well I expect the switch to be closed. because the voltage across it is more than closed...
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