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Can somebody share what are the best techniques in FPGA design that can be used to estimate the logic cell utilisation in an FPGA even before the RTL is written in (VHDL or verilog) so that FPGA selection can be done accordingly to avoid last minute surprises.
Thanks
In which file format do you save the waveform window set up, which can be recalled in the simulation run.
And second thing, as already asked in post #4, how do you relate internal signal names in post layout simulation to the original names in source code
Thanks to both of you..
Both of these solutions proved helpful for behavioral simulation.
But if I am doing post layout simulation the names of all the internal signals changes.
So my query is there any way to trace these names back to the original names used in the source code (VHDL code.)...
Hello
I am running a simulation of a digital design for Virtex 5 FPGA in Modelsim simulator (PE student edition 10.4a).
Currently I am able to trace all the top entity signals in wave window, however I want to trace the internal signals of the design as well,
which are not visible in the...
See there are 2 things --
1. How much maximum weight the weighing machine can sustain ??
That depends on the capacity of the sensor being used which is ultimately decided by your requirements.
2. How much maximum weight the machine can display ??
For that you have to choose the right...
One thing I noticed in your code is that stack_ptr is not there in the process sensitivity list, I am not sure whether till 1000 ns your simulation results are ok or not.
Second thing is since stack grows downwards so the fatal error might be due to negative index of stack_mem, just verify the...
First of all it is important to understand which path in the design is failing, trace it back to RTL code and the verify what are the timing constraints that has been defined for that path in the constraint file.
So to fix it either you have to modify the logic to satisfy the constraints or...
I think logic resources utilized by the design depends on 2 things
1. the FPGA used for design
2. the IDE used to implement the design as different IDE tools uses different optimization algorithms.
The double sampling you have shared works when you are dealing with signals crossing one clock domain and entering into other clock domain.
And in that too clock to be used in the sampling FF should be of the receiving domain.
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