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I have "solved" the issue. I just added pins for the input and output of the resistor and then deleted the warning markers for shorts through the Annotation Browser. I then added the custom resistor to my BGR layout and used 'Define Device Correspondence' option from the 'Connectivity' menu for...
The problem I have right now is the pin designation since the terminals of the resistor I have designed are electrically connected. When I create one of the pins for the resistor, the pin designation 'propagates' through the resistor and sets the same pin designation to the resistor output. How...
I guess there is no problem with that. I am just unsure/don't know how to test my circuitry with my custom created resistor. How can I "tell" Virtuoso that the resistor I have created is actually the resistors presented in the schematic?
Fellow IC designers,
I have a BGR design where I use 5 resistor instances in the circuitry. I want to interdigitate these resistors, however, It is not possible to do this automatically through Virtuoso. I have looked at MODGEN, but for a true interdigitated resistor, I need the fingers of the...
I have solved the issue. The problem was vcvs and vpulse being in the same schematic together. It might be a bug. I have changed the vcvs with an OPAMP I created, which solved the issue. I am using Virtuoso version ICADVM20.1-64b.14.
Thank you all for the help.
Hello,
I have a BGR circuit in schematic. Basically, I want to pull one of the nodes to vdd by utilising an analogLib vpulse connected to an analogLib switch. By this way, the node I want to control would be pulled high periodically and I can observe the circuit's behaviour (theoretically)...
Hello,
I am layouting an OPAMP in Virtuoso and I am using Module Generator to add dummy devices to my transistors. I recently got a warning as follows:
*WARNING* (LCE-2006): The maximum number f opens that can be created on net "GND" has been reached. To change this limit, use the "Maximum...
I am trying to use an spxtswitch component to change between a closed loop and an open loop configuration for an OPAMP in simulation. Basically, inverting input of the OPAMP is connected to either a voltage source (open loop) or the the OPAMP output (closed loop). My questions are as follows...
Hello all,
I am designing a Current Mode Reverse-Bandgap Reference (R-BGR) circuit, with a low supply voltage of 0.8V. I can't comprehend how does the circuit functions (e.g. how does the reference voltage output stays the same) to save my life. Can you give me an explanation for me to...
Hello,
Is there a way to implement a LEF OBS macro in a Python script? I need to have an obstruction rectangle on top of the logo I created on a chip. The logo is created automatically through a Python script. For example, the OBS macro looks like this;
OBS
LAYER LB SPACING 0.04...
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