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Actually , the chain I am talking about is inside the high speed transceiver eval board whose output are directly interfaced with the high speed receiver ADC pins.
That's why I can not test it through VNA.
So, I am asking for any approximate calc that I can done to estimate the phase delay...
Hello support team,
I have 2 different RF chains both can work with 2 GHz RF input but having different Balun, lumped components and matching network. So when I apply same input signal to both RF chains then how can I calculate the phase delay between the 2 chains due to non-identical...
Hello,
Thank you for your quick feedback.
Sorry for typo error in equation: What I am trying to say is that DAC output voltage for 14 bit resolution and 2.5 V ref. voltage = [2.5/16483] * digital input code
And my digital input is having this much of resolution and this range is fixed. so...
Hello,
I am planning to use DAC having the output range of 0 to 10 V with 14 bit resolution. ( if my DAC is having 2.5 V reference voltage)
so, my DAC output voltage will be =[ (2.5)/2^14-1 ]* digital data input
As my digital data input Hex value range is in between : 0x0033 to 0x0FE4 having...
Hello support team,
I have a requirement for 10 MHz clock generation (single ended -sine wave ) for my outdoor unit LNB through FPGA (zynq-7000 series). so is it possible to use below.
40 MHz TCXO interface to Clock capable pin >> Use of clocking wizard for the generation of 10 MHz >> assign...
For I^2+Q^2 , when I am applying -4.7 dBm RF input, below are the max and min value for the conseutive 1,31,072 samples.
Min value (I^2+Q^2) = 0.033015493
Max value (I^2+Q^2) = 0.033976138
Difference in measurement = 0.00096044
For I^2+Q^2 , when I am applying -40 dBm RF input using...
Hello support team,
I have implemented direct conversion method to generate I and Q samples from the RF frequency. and then I am using FPGA IP core to convert I and Q samples to amplitude measurement. I am taking digital samples of measured amplitude.
My input RF-ADC has 14 bit resolution and...
My input sampling rate to divider core is 61.44 MSPS and I am using Divider core with the same clock freq. of 61.44 MHz . that's why I am getting one output divided sample per clock cycle.
In a similar way, my moving average filter input sample rate is 20.48 MSPS and moving average core clock =...
I am looking for the total latency of the averaging algorithm because within 2 usec , my amplitude should measured. and I have calculated used IP cores latency which are 1.4 usec. so i need to figure out the moving averaging total latency(filter delay+ processing time/code)
for the filter...
Ok , so, latency formulla = (No of clock cycles)/clock
4/61.44 *10^6 = 65 nsec
1677212294
I have one doubt then,
If my input sample rate to any IP core is let's say 20 MSPS and If I use the IP core clock to higher let's say at 122.88 MHz. then it will possible to reduce the latency, right?
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