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What the advantage or disadvantage between them when you use:
for me:
OVM: first multi-vendor verification solution, so should be supported well in different simulator.
VMM: looks like faster than others especially for large chip when running in vcs.
What a pity.
However, it's harder to immigrate to canada right now, maybe because the tough economy there. So if I post my request now, canada may accept me after 2 or 3 years latter, I just want to take q queue position there.
Besides, it's more jobs oppotunity here in China, I suggest you...
Maybe you misunderstand my requirement.
I want to generate in [0-0xf], but the item in array must unique.
for example:
there're 3 items in array_my[3] which in [0-0xf];
then I want 0,2,4 or any unique value, but can't be 0,2,2
how to constraint it?
Hi,
In e language, i want generate array_my in [0..0xf] but the item in array don't overlap, does the following rules meet my requirement? If not, how can I generate the non-overlap item in array?
array_my[4] : list of uint;
keep for each in sram_addr_offset {
it in [0..0xf]...
In AMBA PL301, I find the master interface fifo will recorde transaction by pushing when AWVALID and popping when WLAST.
But if I reset the master when AWVALID accepted but WVALID is processing (WLAST isn't come), the master interface will not popping the wrong AWVALID and the fifo is taken if...
set_top +
Hi, littlebu:
Thanks, but just as I mentioned, I could set_top for sub_name, but I cannot use the configuration which set for SE, etc any more, e.g. I [set_top top/A/B], that's right, but [set_constant -type port r:/work/top/SE 0] will be reported error due to cannot find the port...
formality for blackbox
Hi, Sunil:
I think you have some misunderstanding for the subject.
I mean I want to read full design on which the scan and jtag.. configuration based, because the scripts is ready for full design after layout.
But after ECO, I only care a small sub-module consistency...
formality black box
Hi,
When I use formality to verify RTL vs netlist, I have scripts for top, but verify top is a time consuming job when I only want to verify a sub-module (after ECO), for example top/A/B.
Does the formality could do this job easily for my problem? how?
loglong
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