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I'm trying to create a module that stores the contents of a queue, with two parameters, (nmElems) for the number of elements in the queue and (nmBits) for the number of bits in each element. My Verilog code for module (sQueue) is:
// (c) Kevin Simonson 2024
module sQueue #( nmBits = 2, nmElems...
I've built a module (Equ) and a module (t_Equ) to test it, and put it in the upper two windows of EDA Playground. Module (Equ) uses two modules I've already created, (Mux) and (Nt). Module (Mux) itself uses (Nt). The code for (Equ) is:
// (c) Kevin Simonson 2024
module Equ ( result, left...
I took my browser to "https://www.edaplayground.com" to run the EDA playground,
and got a display with four windows. In the window on the left I clicked on
(Tools & Simulators) and selected (Synopsys VCS 2021.09). To the right of that
window, on the bottom was a window that output messages...
Just off the top of my head, say 4 gigabytes, and each of the 4000 processors needs to be able to read from and write to all of it.
1673715592
So are you telling me that, all other things being equal, a computer with 4000 parallel processors is more expensive than a computer with four parallel...
I'm not sure this is the right forum to post this in. Please let me know if there's a better forum I can use. Generally speaking, all other things being equal, is it less expensive to build a computer with four parallel processors (cores, right?) than it is to build a computer with four thousand...
If I've come up with a design for some computer hardware that performs some often needed task that has some advantage over existing hardware or software applications (say in the areas of speed, cost, etc.), can I patent that hardware? If so, how exactly would I do that? It's going to involve a...
I have a piece of code I'm putting together:
module twoDim( hexes, switches);
output [ 7:0] hexes [ 5:0];
input [ 9:0] switches;
// Rest of the file deleted.
endmodule
With this, is (hexes) an array of six values, each of which has eight bits?
Or is it an array of eight values, each...
I've been reading up on carry look ahead adders, and from the diagram on "https://en.wikipedia.org/wiki/Carry-lookahead_adder#/media/File:Four_bit_adder_with_carry_lookahead.svg" I've built the following file:
module ClaFour( cOut, sum, aOp, bOp, cIn);
output cOut;
output [ 3:0] sum...
I've asked questions in this forum about writing Verilog code used in EDA Playground, and had good look getting answers. Is this forum also for questions we have about Quartus? I have succeeded in getting Quartus to download to a FPGA an implementation of a single Verilog file, sometimes with...
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