Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am currently working on a project "AES 128 bits ENCRYPTION DECRYPTION", using Verilog HDL.
Now the problem I am facing is that while simulation- if i provide a plain text all zeros, it gets decrypted perfectly. But when i provide a big number like all ones in plain text, the decryption doesnt...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
