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My understanding that VHDL LS cannot do what yossikr wants. This plug-in will show declaration of the object when you hover over it, but it will not show the actual value of it's not in the declaration.
Imagine you have a constant that contains some matrix, that is calculated using a set of...
I do not see any "if" that can cause latches. All "if"s I see are in clocked always blocks, and they create FFs with clock enables hold the value of the signals when the condition is not satisfied.
@Mario875 I do not see any errors in the part of the code you showed, except for the absence of...
Hi colleagues,
I have a problem meeting timing in my FPGA to FPGA source synchronous DDR data bus.
There are 2 FPGAs on my board and I need to pass data in one direction through a parallel bus. I need it run at 666.666 Mbit/s per lane (32 lanes total), so I use DDR with 333.333 MHz clock. My...
11 different keys generated using key schedule. See https://en.wikipedia.org/wiki/AES_key_schedule and https://en.wikipedia.org/wiki/Advanced_Encryption_Standard for more details.
Interfaces between Verilog and VHDL modules is a gray area that is not really a standard. You basically need to look at your tools and see what they support. They most likely support parameters of the type integer and ports of the type std_logic_vector. So the safest bet whould be to write a...
note that 32'd24 is a 32 bit value, so addr width will be a concatination of 32 bit values.
One possible option is
ADDR_WIDTH => replicate(24, SLAVE_PORTS * MASTER_PORTS)
where replicate is a function you can write to return a vector of needed length with replicated content. But this not going...
You can generate multiport memory with generate loop, but it will be implemented with registers (FFs). Might work for small memories, but it becomes impractical with any significant amount of memory configured.
For muliport memory of significant sizes you need a much more complicated design...
Yes, it is a problem, because always block is not clocked. As you may see, it has all the signals in its sensitivity list @(*) as opposed to @(posedge clk).
When you have a signal that is "self referenced" you have a combinatorial (logic/timing) loop. Try to imagine how would behave an actual...
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