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If I understood correctly, the DQM needs to be set three cycles before when doing burst. But as said, forcing the DQM signals *always* to be either high or low, has no effect on neither reads nor writes. On writes, all bytes are written, on reads, all bytes are read and they never show High-Z...
My controller sets the DQM lines but there doesn't seem to be any effect to neither writes nor reads. Regardless whether the controller sets them high or low or any combination of them, the writes will always write all 32 bits to SDRAM, and reads will always return a value where none of the...
I've made an SDRAM controller unit in Verilog for Altera DE2-115 but it seems that the byte enable signals DRAM_DQM[3:0] do not actually do anything, at least on my board. Regardless whether they're set high or low, the writes and reads result in a 32 bit write or read even though they are...
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