Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If I want to inject the current pulse same as in attached fig, is it possible in cadence virtuso (with LET values)??
If so, how to give this pulse using cadence virtuoso with LET values???
{image file taken from book "Soft Errors: from particles to circuits" }
Can we calculate collected charge (Qcoll) from the constants specified in isource i.e, constants such as rise time constant, fall time constant, rise time and fall time.?? I am attaching a image file for your ref.
**broken link removed**
I need to find single event transient in circuit level...
Hi,
I am designing a circuit in cadence virtuoso. I want to do the single event upset in a node.
Can anyone tell me the simulation procedure to include it in cadence circuit simulator?
Thanks in advance..
Hai
I am trying to get WNM of SRAM. I am following the procedure given in the book "Robust SRAM designs and analysis". I have attached the WNM graph (Fig1_WNM_book) from this book.
My doubt is:
As per the procedure, BL line is connected to Vdd and BLB line is connected to gnd. The voltage at...
Re: 32nm finfet hspice model
Hai,
Can I use this same FinFET model for LNA and Mixer simulation?
Will it work for independent gate inputs? (means g1 for RF input and g2 for LO input)
If anyone did the FinFET I-V characteristics, pls suggest me. I want to plot a graph Id- Vg1 for different Vg2...
Hai,
Anyone know about the InAs Tunnel FET (given by Penn State Univ) TCAD simulation??? How to get the same result as per their look up table?
Pls help me.
hai,
I'm trying to do Sdevice simulation of InAs Tunnel FET given by Penn State Univesity. im getting Id value in microamperes.
Have anyone tried with InAs TFET simulation? If you are getting same result as they gave in lookup table, pls help me also.
Hai everyone,
Currently, i'm working in sentaurus TCAD workbench. First, I have added a tool "SDE" in which I added several parameters and their values. Then I have added the tools like Sdevice, Inspect..
When i run those nodes, no error occur. Then I added a second value for a parameter...
Hai Everyone,
In conventional mixer, since the mixing stage is acting as switch, the biasing voltage should be below the threshold voltage. if it is so, how the transconductance stage is acting in Saturation region?
Vds to the transconductance stage is less than the biasing voltage (Vgs). Is...
Ok thanks @Dominik.. i don't have tsmc180 now. thats why im asking, Is there any diff? As you said, if the model parameters are completely different for both 180nm, we can't get the approximate results.
Hai ,
Is there any difference between gpdk180 and tsmc180 in the model parameters? can we get approximate simulation results, when using gpdk180 instead of tsmc180???? plz reply asap.
Thank you :smile:
hai,
when i use fingers for transistor, there is a mismatch error b/w Layout vs Schematic. In inverter circuit, i used 2 fingers for both nmos nd pmos. after completing the layout design, during LVS check, mismatch error appeared. how to resolve this?
the error is:
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
